公开(公告)号：US20230115776A1

公开(公告)日：2023-04-13

申请号：US17900228

申请日：2022-08-31

申请人： RENESAS ELECTRONICS CORPORATION

发明人： Haruyuki OKUDA

IPC分类号： G11C29/12 ,  G11C11/418

摘要： A semiconductor device includes memory cells, word lines, a row address decoder, word line drivers, a first switch transistor, and second switch transistors. The switch transistor is provided between the word line drivers and a power supply potential terminal. Each second switch transistor is provided between each word line and a reference potential terminal. The row address decoder activates all of decode signals corresponding to the memory cells to which a burn-in test is performed collectively. The first switch transistor has a lower driving capability than a total driving capability of two P-channel MOS transistors included in inverters of two word line drivers. Each second switch transistor has a lower driving capability than a driving capability of an N-channel MOS transistor included in the inverter of each word line driver.

公开(公告)号：US11626159B2

公开(公告)日：2023-04-11

申请号：US17336451

申请日：2021-06-02

申请人： Korea University Research and Business Foundation

发明人： Jongsun Park ,  Kyeongho Lee ,  Woong Choi

IPC分类号： G11C11/419 ,  G11C11/418

摘要： A computing in-memory device includes a memory cell array supporting a bitwise operation through at least one pair of memory cells activated in response to at least one pair of word line signals and a peripheral circuit connected to the at least one pair of memory cells via one pair of bit lines and performing a discharging operation on at least one bit line of the one pair of bit lines based on a voltage level of the one pair of bit lines.

公开(公告)号：US11621258B2

公开(公告)日：2023-04-04

申请号：US17122652

申请日：2020-12-15

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Shih-Lien Linus Lu

IPC分类号： G11C11/412 ,  G11C11/418 ,  G11C11/419 ,  H01L27/02 ,  H01L27/11

摘要： A memory circuit includes a first word line, a first and second bit line, a first and second inverter, a P-type pass gate transistor and a pre-charge circuit. The first word line extends in a first direction. The first and second bit line extend in a second direction. The first inverter has a first storage node coupled to the second inverter. The second inverter has a second storage node coupled to the first inverter, and is not coupled to the second bit line. The P-type pass gate transistor is coupled between the first storage node and the first bit line. The pre-charge circuit is coupled to the first or second bit line, and is configured to charge the first or second bit line to a pre-charge voltage responsive to a first signal. The pre-charge voltage is between a voltage of a first logical level and a second logical level.

公开(公告)号：US11621035B1

公开(公告)日：2023-04-04

申请号：US17447841

申请日：2021-09-16

申请人： GlobalFoundries U.S. Inc.

发明人： Vivek Raj ,  Vinayak Rajendra Ganji ,  Shivraj Gurpadappa Dharne

IPC分类号： G11C8/10 ,  G11C11/418 ,  G11C11/419 ,  G11C8/08 ,  G11C7/10

摘要： Embodiments of the present disclosure provide a memory circuit structure including a transistor array for writing a plurality of bits to a memory element. The transistor array includes a first transistor having a first source/drain terminal for receiving a supply voltage. A first word line is coupled between a decoder and the first source/drain terminal of the first transistor. The first word line transmits a voltage output from the decoder to the first transistor as the supply voltage.

公开(公告)号：US11605422B2

公开(公告)日：2023-03-14

申请号：US17332753

申请日：2021-05-27

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Shih-Lien Linus Lu

IPC分类号： G11C16/04 ,  G11C11/418 ,  G11C11/419 ,  G11C8/10 ,  G11C7/08 ,  G11C11/412

摘要： A circuit includes a memory array, a control circuit configured to identify an address of a first row containing a weak cell, and store corresponding address information in a storage device, and an address decoding circuit including NAND pairs, inverter pairs, and a logic tree. Each NAND pair receives corresponding bits of the address information and the address of the first row and corresponding inverted bits of the address information and the address of the first row inverted by corresponding inverter pairs, and output terminals of the NAND pairs are connected to the logic tree. The logic tree matches the address information with the address of the first row based on output logic levels from the NAND pairs and, in response to the corresponding address information matching the address of the first row, activates a second row of the memory array simultaneously with the first row being activated.

公开(公告)号：US20230065165A1

公开(公告)日：2023-03-02

申请号：US17554838

申请日：2021-12-17

申请人： Meta Platforms Technologies, LLC

发明人： Edith DALLARD ,  Huichu LIU ,  Daniel Henry MORRIS ,  Doyun KIM

IPC分类号： G11C11/419 ,  G11C11/418

摘要： In some embodiments, an apparatus comprises: a static random access memory (SRAM) device. The SRAM device may have a bit cell array comprising a plurality of bit cells, the plurality of bit cells arranged in a plurality of rows and a plurality of columns, each column of the plurality of columns operatively coupled to a pair of bit lines. The apparatus may comprise a controller configured to: assert a word line associated with a row; perform a sequence of write operations while the word line remains asserted, each write operation corresponding to a bit cell associated with a different column of the plurality of columns and the row, wherein the word line has an elevated voltage relative to a non-elevated voltage during at least a portion of the sequence of write operations; and de-assert the word line after the sequence of write operations are performed.

公开(公告)号：US11568951B2

公开(公告)日：2023-01-31

申请号：US16817096

申请日：2020-03-12

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Francisco Adolfo Cano ,  Devanathan Varadarajan ,  Anthony Martin Hill

IPC分类号： G11C29/00 ,  G11C29/38 ,  G11C29/50 ,  G11C11/419 ,  G11C11/418 ,  G11C11/412

摘要： Systems and methods of screening memory cells by modulating bitline and/or wordline voltage. In a read operation, the wordline may be overdriven or underdriven as compared to a nominal operating voltage on the wordline. In a write operation, the one or both of the bitline and wordline may be overdriven or underdriven as compared to a nominal operating voltage of each. A built-in self test (BIST) system for screening a memory array has bitline and wordline margin controls to modulate bitline and wordline voltage, respectively, in the memory array.

公开(公告)号：US11568925B2

公开(公告)日：2023-01-31

申请号：US17084880

申请日：2020-10-30

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Sanjeev Kumar Jain

IPC分类号： G11C11/418 ,  G11C11/419 ,  G11C11/412

摘要： A memory device is disclosed. The memory device includes a memory array including a first memory cell arranged in a first row and a first column and a second memory cell arranged in the first row and a second column next to the first column. The first memory cell is configured to perform a write operation in response to a first write signal transmitted through a first write word line. The second memory cell is configured to perform the write operation in response to a second write signal transmitted through a second write word line. The second write word line is separated from and next to the first write word line. The first write signal and the second write signal have different logic values.

公开(公告)号：US20230008833A1

公开(公告)日：2023-01-12

申请号：US17849903

申请日：2022-06-27

申请人： STMicroelectronics International N.V.

发明人： Harsh RAWAT ,  Kedar Janardan DHORI ,  Promod KUMAR ,  Nitin CHAWLA ,  Manuj AYODHYAWASI

IPC分类号： G11C11/418

摘要： SRAM cells are connected in columns by bit lines and connected in rows by first and second word lines coupled to first and second data storage sides of the SRAM cells. First the first word lines are actuated in parallel and then next the second word lines are actuated in parallel in first and second phases, respectively, of an in-memory compute operation. Bit line voltages in the first and second phases are processed to generate an in-memory compute operation decision. A low supply node reference voltage for the SRAM cells is selectively modulated between a ground voltage and a negative voltage. The first data storage side receives the negative voltage and the second data storage side receives the ground voltage during the second phase. Conversely, the second data storage side receives the negative voltage and the first data storage side receives the ground voltage during the first phase.

公开(公告)号：US11552084B2

公开(公告)日：2023-01-10

申请号：US17248112

申请日：2021-01-08

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Ping-Wei Wang ,  Chih-Chuan Yang ,  Lien Jung Hung ,  Feng-Ming Chang ,  Kuo-Hsiu Hsu ,  Kian-Long Lim ,  Ruey-Wen Chang

IPC分类号： H01L27/11 ,  G11C11/41 ,  H01L23/528 ,  H01L29/06 ,  G11C11/418 ,  H01L29/786 ,  H01L29/66 ,  H01L29/423

摘要： Methods and devices including a plurality of memory cells and a first bit line connected to a first column of memory cells of the plurality of memory cells, and a second bit line connected to the first column of cells. The first bit line is shared with a second column of memory cells adjacent to the first column of memory cells. The second bit line is shared with a third column of cells adjacent to the first column of cells opposite the second column of cells.