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1.发明公开公开(公告)号：US20230318577A1
公开(公告)日：2023-10-05
申请号：US18182571
申请日：2023-03-13
发明人： Seon-Ho HAN , Bon Tae KOO
摘要： Disclosed is a phase shift circuit including an input circuit for generating first to fourth internal signals based on an in-phase signal, a complementary in-phase signal, a quadrature phase signal, and a complementary quadrature phase signal and a switching circuit for outputting first to fourth shift signals based on the first to fourth internal signals. The input circuit includes a first transistor connected between a ground node and a first node to operate based on the in-phase signal and the first bias signal, a second transistor connected between the ground node and a second node to operate based on the complementary in-phase signal and the first bias signal, a third transistor connected between the ground node and the first node to operate based on the second bias signal, and a fourth transistor connected between the ground node and the second node to operate based on the second bias signal.
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公开(公告)号：US20170317682A1
公开(公告)日：2017-11-02
申请号：US15497648
申请日：2017-04-26
发明人： Yuji SHIMIZU , Akane HIROSHIMA , Yutaka ONO
摘要： A control apparatus includes, for at least two-phase signals detected from a resolver excited by a carrier signal having a carrier frequency fc, a first phase shifter that shifts a phase of a first phase signal of the resolver with a pole at a frequency f1 lower than the carrier frequency fc, a second phase shifter that shifts a phase of a second phase signal of the resolver with a pole at a frequency f2 higher than the carrier frequency fc, a signal generator that generates a correction signal for canceling out an error component of the carrier signal, and a synthesizer that synthesizes the phase-shifted first phase signal, the phase-shifted second signal, and the correction signal for canceling out the error component, in order to create a phase-modulated signal that is the carrier signal being modulated at a rotation angle of a rotor of the resolver.
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公开(公告)号：US09614498B2
公开(公告)日：2017-04-04
申请号：US15103403
申请日：2014-02-26
摘要： An active balun circuit includes a CG transistor having a source terminal thereof connected to an input terminal and a gate terminal thereof grounded, a CS transistor having a gate terminal thereof connected to the input terminal and a source terminal thereof grounded, an asymmetrical transformer, a first output terminal, and a second output terminal. The asymmetrical transformer includes a primary coil and a secondary coil. The primary coil includes a first inductor connected to the CG transistor and a second inductor connected to the CS transistor. The secondary coil includes a third inductor associated with the first inductor and a fourth inductor associated with the second inductor. The first output terminal outputs a first signal generated at the third inductor, and the second output terminal outputs a second signal generated at the fourth inductor.
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公开(公告)号：US20160301388A1
公开(公告)日：2016-10-13
申请号：US14806478
申请日：2015-07-22
发明人： John Perry Myers
CPC分类号： H03H11/18 , H03B27/00 , H03D3/009 , H03D7/1441 , H03D7/1458 , H03D2200/0021 , H03D2200/0043 , H03H11/22 , H03K5/02 , H03K5/26 , H03K2005/00286
摘要： A method and system of compensating for phase error. A phase error compensation circuit is configured to generate a phase-corrected quadrature Q output signal and a corresponding phase-corrected in-phase I output signal, the circuit includes a first transconductance circuit configured to convert a voltage signal related to an I input voltage signal to an I current signal. A second transconductance circuit is configured to convert a voltage signal related to a Q input signal to a Q current signal. A first multiplier circuit is configured to multiply the Q current signal times a Q scaling constant. A second multiplier circuit is configured to multiply the I current signal times an I scaling constant. An I summer sums the I current signal with the scaled Q signal. A Q summer sums the Q current signal with the scaled I signal.
摘要翻译： 一种补偿相位误差的方法和系统。 相位误差补偿电路被配置为产生相位校正的正交Q输出信号和对应的相位校正的同相I输出信号，该电路包括第一跨导电路，其被配置为将与I输入电压信号相关的电压信号 到I当前信号。 第二跨导电路被配置为将与Q输入信号相关的电压信号转换为Q电流信号。 第一乘法器电路被配置为将Q电流信号乘以Q缩放常数。 第二乘法器电路被配置为将I电流信号乘以I缩放常数。 I夏天用缩放的Q信号来计算I电流信号。 Q夏天与缩放的I信号相加Q电流信号。
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公开(公告)号：US5963073A
公开(公告)日：1999-10-05
申请号：US751730
申请日：1996-11-18
申请人： Kenji Fujita , Hiroshi Takeuchi
发明人： Kenji Fujita , Hiroshi Takeuchi
IPC分类号： H03K23/00 , H03H11/18 , H03H11/22 , H03K5/15 , H03L7/06 , H04J11/00 , H03K3/286 , H03K5/13 , H03L7/00
CPC分类号： H03K5/1506
摘要： The invention is directed to the realization of a .pi./2 phase shifter that provides accurate operation and moreover enables a reduction in current consumption. Such a .pi./2 phase shifter is constructed from a 1/2-frequency divider employing a T flip-flop and includes: a current source circuit which supplies to the T flip-flop a circuit current that determines the output frequency of the T flip-flop and which varies circuit current value according to control signals; and a frequency comparator that compares the output frequency of the T flip-flop and the local signal input frequency, and, based on the comparison results, varies the control signals in a direction such that the output frequency of the T flip-flop matches the local signal input frequency.
摘要翻译： 本发明旨在实现提供精确操作的pi / 2移相器，并且还能够降低电流消耗。 这种π/ 2移相器由采用T触发器的1/2分频器构成，并包括：电流源电路，向T触发器提供确定T触发器的输出频率的电路电流 并根据控制信号改变电路电流值; 以及频率比较器，其比较T触发器的输出频率和本地信号输入频率，并且基于比较结果，改变控制信号，使得T触发器的输出频率与 本地信号输入频率。
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公开(公告)号：US5914623A
公开(公告)日：1999-06-22
申请号：US848486
申请日：1997-05-08
申请人： Kenji Fujita
发明人： Kenji Fujita
CPC分类号： H03H11/18
摘要： A 90.degree.-phase shifter which operates in condition both of high-speed and low dissipation power, and an output signal with precise 90.degree.-phase difference is capable of taking off is provided. It causes input signals with complementary relation each other to input toward input terminals. A 1/2 frequency divider is composed of bi-differential transistors Tr5 to Tr12, and load resistances R1 to R4. The 1/2 frequency divider outputs a 90.degree.-phase difference signal to output terminals 11 to 14 based on collector current of signal input transistors Tr1 and Tr2. The collector current corresponds to the input signal. A duty ratio monitoring load 2 converts these collector currents into voltage. A low-pass filter 3 takes off a DC component corresponding to an offset from 50%-duty ratio of an input voltage from the converted voltage. A DC component amplifier amplifies the DC component thus performing feedback to the input terminals 8 and 9. For this reason, the duty ratio of the collector current of the signal input transistors Tr1 to Tr2 comes precisely into 50%.
摘要翻译： 提供在高速和低功耗条件下工作的90°移相器，并提供具有90°相位差精度的输出信号。 使彼此互补的输入信号向输入端子输入。 1/2分频器由双差分晶体管Tr5至Tr12以及负载电阻R1至R4组成。 + E，fra 1/2 + EE分频器基于信号输入晶体管Tr1和Tr2的集电极电流向输出端子11至14输出90°相位差信号。 集电极电流对应于输入信号。 占空比监测负载2将这些集电极电流转换为电压。 低通滤波器3取出与转换电压的输入电压的50％占空比相对应的直流成分。 DC分量放大器放大DC分量，从而对输入端子8和9进行反馈。因此，信号输入晶体管Tr1至Tr2的集电极电流的占空比精确地达到50％。
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7.发明授权
公开(公告)号：US5808498A
公开(公告)日：1998-09-15
申请号：US891128
申请日：1997-07-10
申请人： Kevin S. Donnelly , Pak Shing Chau
发明人： Kevin S. Donnelly , Pak Shing Chau
CPC分类号： H03L7/0812 , H03H11/18 , H03K5/133 , H03K5/151 , H03K2005/00208
摘要： A phase shifting circuit that may be used as part of a quadrature clock generator. The phase shifting circuit comprises a triangle wave generator coupled to receive an input reference signal. The triangle wave generator outputs a pair of complementary triangle wave signals in response to the input reference signal. A comparator having a pair of inputs is coupled to receive the pair of complementary triangle wave signals. The comparator outputs an output signal having a predetermined phase relationship with the input reference signal in response to a comparison between the pair of complementary triangle wave signals.
摘要翻译： 可用作正交时钟发生器的一部分的移相电路。 相移电路包括耦合以接收输入参考信号的三角波发生器。 三角波发生器响应于输入参考信号输出一对互补三角波信号。 具有一对输入的比较器被耦合以接收该对互补三角波信号。 响应于一对互补三角波信号之间的比较，比较器输出与输入参考信号具有预定相位关系的输出信号。
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公开(公告)号：US5644260A
公开(公告)日：1997-07-01
申请号：US542745
申请日：1995-10-13
IPC分类号： H03H7/20 , H03C1/02 , H03C1/52 , H03C1/60 , H03C3/00 , H03C3/40 , H03C5/00 , H03D1/22 , H03D3/00 , H03H7/21 , H03H11/16 , H03H11/18 , H03H11/22 , H04L27/20 , H04L27/36
CPC分类号： H03C5/00 , H03C1/52 , H03C3/00 , H03C3/40 , H03H11/16 , H03H11/18 , H03H11/22 , H03C1/02 , H03C1/60 , H03C2200/0016 , H03C2200/0058 , H03D1/2245 , H03D3/007
摘要： An IQ modulator incorporates a quadrature network that is responsive to a frequency dependent control signal and that has in-phase and quadrature signals that are of equal amplitude and in exact quadrature over a wide range of applied frequencies. The quadrature network includes RC and CR phase shifters whose C's are fixed capacitors of equal value and whose R's are made equal to each other and to the capacitive reactance of the C's by the action of the frequency dependent control signal. The R's may be FET's. The frequency dependent control signal may be generated without express knowledge of the applied frequency by a servo loop that nulls out the amplitude difference between the in-phase and quadrature outputs from the quadrature network; it may also be generated from a look-up table as an express function of frequency. The frequency dependent control signal is split into separate instances that are applied to each R, and an offset may be introduced therebetween to provide extreme precision. The offset may be fixed or programmatically controlled as a function of frequency. Varactors may be used to provide variable C's in cooperation with fixed R's. The entire circuit may be fabricated as a GaAs IC for use in the frequency range of 200 MHz to 3 GHz.
摘要翻译： IQ调制器包括正交网络，该正交网络响应于频率相关的控制信号，并且具有同相和正交信号，它们在宽的施加频率范围内具有相等幅度和准确的正交。 正交网络包括RC和CR相移器，其C是相等值的固定电容器，并且R通过频率相关控制信号的作用使得R相互相等并且与C的容性电抗相对应。 R的可能是FET的。 频率相关控制信号可以在没有通过伺服环路的应用频率的明确知识的情况下产生，从而消除来自正交网络的同相和正交输出之间的幅度差异; 它也可以从查找表生成为频率的表达功能。 频率相关控制信号被分割成分别应用于每个R的实例，并且可以在其间引入偏移以提供极高的精度。 偏移可以是固定的或者作为频率的函数被编程地控制。 Varactors可以用于与固定R协作提供变量C。 整个电路可以被制造为在200MHz至3GHz的频率范围内使用的GaAs IC。
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公开(公告)号：US5642427A
公开(公告)日：1997-06-24
申请号：US420365
申请日：1995-04-11
申请人： Joel Katz , Miles Kath
发明人： Joel Katz , Miles Kath
摘要： An integrated circuit for use as a building block in different embodiments of systems for enhancing audio performance by providing group delay to various frequency components of the signal. The integrated circuit includes four op amps and associated circuitry. Using external connections, the device can be configured as a two-channel stereo device, or can be cascaded for monaural applications. Two of the chips may be cascaded together for stereo applications. External capacitances and resistances are used to control the degree of group delay provided to the signal to realize desired audio enhancement.
摘要翻译： 一种集成电路，用作系统的不同实施例中的构建块，用于通过向信号的各种频率分量提供组延迟来增强音频性能。 集成电路包括四个运算放大器和相关电路。 使用外部连接，该设备可以配置为双通道立体声设备，也可以级联用于单声道应用。 两个芯片可以级联在一起用于立体声应用。 外部电容和电阻用于控制提供给信号的群延迟的程度以实现所需的音频增强。
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公开(公告)号：US5489873A
公开(公告)日：1996-02-06
申请号：US395136
申请日：1995-02-27
申请人： Takatsugu Kamata , Jun Takahashi
发明人： Takatsugu Kamata , Jun Takahashi
CPC分类号： H03D3/22 , H03H11/1252 , H03H11/18 , H03D2200/0047 , H03D2200/0082 , H03D3/02
摘要： An active low-pass filter suitable as a 90.degree. phase shifter circuit is provided which requires few external components when formed as an IC. The current resulting from the input signal outputted from a first impedance element is amplified by a first current amplifier, and the resulting output current is converted by a first converting means to a voltage, which is supplied via a second impedance element to a second current amplifier; the output current of the second current amplifier is converted by a second converting means to a voltage, which is outputted as a filter output, while the current corresponding to the output voltage of the second converting means is negatively fed back into the inputs of the first and second current amplifiers; furthermore, at least the current amplification factor of the first current amplifier is made controllable, thereby permitting the cut-off frequency to be varied arbitrarily.
摘要翻译： 提供适合作为90°移相器电路的有源低通滤波器，当形成IC时需要很少的外部元件。 由第一阻抗元件输出的输入信号产生的电流由第一电流放大器放大，并且所得到的输出电流由第一转换装置转换成经由第二阻抗元件提供给第二电流放大器的电压 ; 第二电流放大器的输出电流由第二转换装置转换成作为滤波器输出输出的电压，而对应于第二转换装置的输出电压的电流被负反馈回第一转换装置的输入端 和第二电流放大器; 此外，至少使第一电流放大器的电流放大系数可控，从而允许截止频率任意变化。
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