公开(公告)号：US11637527B2

公开(公告)日：2023-04-25

申请号：US17618064

申请日：2019-06-12

申请人： The General Hospital Corporation ,  Board of Trustees Michigan State University

发明人： Xin Yu ,  Chunqi Qian

IPC分类号： H03B5/12 ,  H03J3/18 ,  H03L7/099 ,  G01R33/36 ,  G01R33/48

摘要： The multi-modal imaging system, in particular for brain imaging, comprising a pump signal generator which emits at least one pump signal in the radio frequency (RF)-range with a first power P1 and a second power P2, a wireless detection unit, which comprises at least one parametric resonator circuit with multiple resonance modes, wherein the at least one parametric resonator circuit comprises at least two varactors, at least one capacitor and at least one inductance, wherein, in a first detection mode, the pump signal, having a first power P1, induces a first pump current in the at least one parametric resonator circuit, wherein the at least one parametric resonator circuit is operated below its oscillation threshold and generates a first output signal by amplifying a first input signal, which is provided due to a magnetic-resonance (MR) measurement, wherein an external receiving device receives the first output signal, wherein, in a second detection mode, the pump signal, having a second power P2, induces a second pump current in the at least one parametric resonator circuit, wherein the at least one parametric resonator circuit is operated above its oscillation threshold and generates a second output signal, wherein the second output signal is modulated with a second input signal, wherein the second input signal is provided by at least one neuronal probe device, connected to the at least one parametric resonator circuit, wherein the external receiving device receives the second output signal.

公开(公告)号：US20190074325A1

公开(公告)日：2019-03-07

申请号：US15963379

申请日：2018-04-26

申请人： Her Majesty the Queen in Right of Canada, as represented by the Minister of Industry, through

发明人： Khelifa HETTAK ,  Jafar SHAKER ,  Aldo PETOSA ,  Jonathan ETHIER ,  Reza CHAHARMIR ,  Ming LI ,  Nicolas GAGNON

IPC分类号： H01L27/28 ,  H01L49/02 ,  H03J3/20 ,  H01G7/06 ,  H01L21/84 ,  H01L21/288 ,  H01L21/02 ,  H01L51/00 ,  H03J3/18 ,  H01L29/93

摘要： An electronic component such as a voltage controllable reconfigurable capacitor or transistor is formed by printing one or more layers of ink on a non-conductive substrate. Ferroelectric ink or semi-conductive ink is printed and conductive resistive or dielectric ink is printed on a s same or different layers. Reconfigurability is achieved by printing resistive biasing circuitry wherein when a changing voltage is applied to the biasing circuitry, an electronic property of the electronic component changes in response to the changing voltage.

公开(公告)号：US10211779B2

公开(公告)日：2019-02-19

申请号：US15151786

申请日：2016-05-11

申请人： International Business Machines Corporation

发明人： Mark A. Ferriss ,  Daniel J. Friedman ,  Bodhisatwa Sadhu ,  Alberto Valdes-Garcia

IPC分类号： H03B5/12 ,  H03B7/06 ,  H03J3/18 ,  H03J3/20 ,  H03J3/22 ,  H03J5/02 ,  H03L7/099

摘要： A voltage controlled oscillator comprises a negative resistance, a first inductor, a fixed capacitor, and a frequency control component. The frequency control component comprises at least one varactor and at least a second inductor connected in series with the at least one varactor. A magnitude of an inductance of the second inductor is selected such that the frequency control component has an effective capacitance range larger than a capacitance range of the at least one varactor.

公开(公告)号：US20050287970A1

公开(公告)日：2005-12-29

申请号：US11157579

申请日：2005-06-21

申请人： Masaki Yamamoto

发明人： Masaki Yamamoto

IPC分类号： H03J3/18 ,  H03J3/32 ,  H04B1/18

CPC分类号： H03J3/185 ,  H03J3/32 ,  H03J2200/36 ,  H03J2200/37 ,  H03J2200/38

摘要： A television tuner includes a tuning circuit having two first varactor diodes for changing a tuning frequency, a mixer for converting a television signal to an intermediate frequency signal, an oscillator having a second varactor diode, and a PLL circuit for outputting a tuning voltage for tuning the television signal. The tuning voltage is applied to cathodes of the first varactor diodes and the second varactor diode, and voltages of anodes of the first varactor diodes and the second varactor diode are higher at a time of receiving the television signal whose frequency is lower than or equal to a predetermined frequency than at a time of receiving a television signal whose frequency is higher than the predetermined frequency.

摘要翻译： 电视调谐器包括具有两个用于改变调谐频率的第一变容二极管的调谐电路，用于将电视信号转换成中频信号的混频器，具有第二变容二极管的振荡器和用于输出用于调谐的调谐电压的PLL电路 电视信号。 调谐电压施加到第一变容二极管和第二变容二极管的阴极，并且在接收频率低于或等于的电视信号时，第一变容二极管和第二变容二极管的阳极的电压较高 比接收频率高于预定频率的电视信号时的预定频率。

公开(公告)号：US20050258901A1

公开(公告)日：2005-11-24

申请号：US11131281

申请日：2005-05-18

申请人： Haideh Khorramabadi

发明人： Haideh Khorramabadi

IPC分类号： H01F17/00 ,  H01L23/522 ,  H01L27/02 ,  H01L27/08 ,  H03B1/00 ,  H03B5/12 ,  H03B5/36 ,  H03D7/16 ,  H03D7/18 ,  H03G1/00 ,  H03H11/12 ,  H03J1/00 ,  H03J3/04 ,  H03J3/08 ,  H03J3/18 ,  H03L1/02 ,  H03L7/10 ,  H03L7/23 ,  H03F3/45

CPC分类号： H03L7/23 ,  H01F17/0006 ,  H01F17/0013 ,  H01F2017/0053 ,  H01F2021/125 ,  H01L23/5227 ,  H01L27/0248 ,  H01L27/08 ,  H01L2924/0002 ,  H01L2924/3011 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/364 ,  H03B2201/025 ,  H03B2201/0266 ,  H03D7/161 ,  H03D7/18 ,  H03F1/3211 ,  H03F1/52 ,  H03F3/191 ,  H03F3/45183 ,  H03F3/45188 ,  H03F3/45475 ,  H03F2200/294 ,  H03F2203/45318 ,  H03F2203/45704 ,  H03G1/0029 ,  H03H11/1291 ,  H03J1/0075 ,  H03J3/04 ,  H03J3/08 ,  H03J3/185 ,  H03J2200/10 ,  H03L1/023 ,  H03L7/10 ,  H03L7/18 ,  H01L2924/00

摘要： An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit. A receiver front end provides programable attenuation and a programable gain low noise amplifier. LC filters integrated onto the substrate in conjunction with image reject mixers provide image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. Active filters utilize multi track spiral inductors with shields to increase circuit Q. The filters incorporate a gain stage that provides improved dynamic range through the use of cross coupled auxiliary differential pair CMOS amplifiers to cancel distortion in a main linearized differential pair amplifier. Frequency planning provides additional image rejection. Local oscillator signal generation methods on chip reduce distortion. A PLL generates needed out of band LO signals. Direct synthesis generates in band LO signals. PLL VCOs are centered automatically. A differential crystal oscillator provides a frequency reference. Differential signal transmission throughout the receiver is used. ESD protection is provided by a pad ring and ESD clamping structure. Shunts utilize a gate boosting at each pin to discharge ESD build up. An IF VGA utilizes distortion cancellation achieved with cross coupled differential pair amplifiers having their Vds dynamically modified in conjunction with current steering of the differential pairs sources.

摘要翻译： 具有通道选择和图像抑制的集成接收器基本上在单个CMOS集成电路上实现。 接收机前端提供可编程衰减和可编程增益低噪声放大器。 与图像抑制混合器一起集成到衬底上的LC滤波器提供图像频率抑制。 过滤器调谐和电感Q补偿温度在芯片上执行。 有源滤波器利用具有屏蔽的多轨螺旋电感器来增加电路Q.滤波器包括增益级，其通过使用交叉耦合辅助差分对CMOS放大器来消除主线性化差分对放大器中的失真而提供改进的动态范围。 频率规划提供额外的镜像抑制。 本地振荡器信号产生方法在芯片上减少失真。 PLL产生所需的带外LO信号。 直接合成产生带内LO信号。 PLL VCO自动居中。 差分晶体振荡器提供频率参考。 使用整个接收机的差分信号传输。 ESD保护由衬垫环和ESD夹紧结构提供。 分流器利用每个引脚上的门极升压来放电ESD积聚。 IF VGA利用交叉耦合的差分对放大器实现的失真消除，其具有与差分对源的当前转向结合动态修改的V ds。

公开(公告)号：US06950152B2

公开(公告)日：2005-09-27

申请号：US10271922

申请日：2002-10-16

申请人： Masaki Yamamoto

发明人： Masaki Yamamoto

IPC分类号： H03J3/18 ,  H03J5/24 ,  H04N5/50

CPC分类号： H03J3/185 ,  H03J5/244

摘要： A gain deviation is leveled in the same band by using a varactor diode having the same characteristics as that used in an input tuning circuit for coupling the input tuning circuit and a high frequency amplifier The input tuning circuit has a tuning varactor diode whose tuning frequency varies with a tuning voltage applied to the cathode of the tuning varactor diode, a high-frequency amplifier is provided in a stage subsequent to the input tuning circuit, and a coupling varactor diode for coupling the input tuning circuit to the high-frequency amplifier, in which the cathode of the coupling varactor diode and that of the tuning varactor diode are connected with each other and a bias voltage higher than the voltage at the anode of the tuning varactor diode and lower than the lowest voltage of the tuning voltage is applied to the anode of the coupling varactor diode.

摘要翻译： 通过使用与用于耦合输入调谐电路和高频放大器的输入调谐电路中使用的特性相同的变容二极管，在相同频带中增益偏移。输入调谐电路具有调谐变换二极管，其调谐频率变化 施加到调谐变容二极管的阴极的调谐电压，在输入调谐电路之后的级中提供高频放大器，以及用于将输入调谐电路耦合到高频放大器的耦合变容二极管， 其中耦合变容二极管的阴极和调谐变容二极管的阴极彼此连接，并且偏置电压高于调谐变容二极管的阳极处的电压并且低于调谐电压的最低电压，施加到 耦合变容二极管的阳极。

公开(公告)号：US20050189999A1

公开(公告)日：2005-09-01

申请号：US11025781

申请日：2004-12-29

申请人： Andreia Cathelin ,  Stephane Razafimandimby ,  Didier Belot ,  Jean-Francois Carpentier

发明人： Andreia Cathelin ,  Stephane Razafimandimby ,  Didier Belot ,  Jean-Francois Carpentier

IPC分类号： H03B5/36 ,  H03J3/18 ,  H03J3/20 ,  H03J3/24 ,  H03L5/00 ,  H03L7/00 ,  H03L7/099

CPC分类号： H03L7/0805 ,  H03B5/366 ,  H03H2009/02204 ,  H03J3/185 ,  H03J3/20 ,  H03J3/22 ,  H03J3/24 ,  H03L5/00 ,  H03L7/00 ,  H03L7/099

摘要： An integrated electronic circuit comprises at least first and second variable resonator elements that can be tuned by means of an electric signal (Vtune) and that are arranged on the same silicon substrate, and that are respectively integrated into a Master circuit and a Slave circuit. Each resonator element is associated with a first inductive partner element set in the vicinity of the resonant and antiresonant frequencies; and with a second capacitive partner element, at least one of said partner elements being adjustable by means of said electric signal (Vtune). Controlling both partner elements could be done either by means of an adjustable capacitor, as a varactor, or by means of an inductor, passive or active, fixed or variable.

摘要翻译： 集成电子电路包括至少第一和第二可变谐振器元件，其可以通过电信号（V调谐）进行调谐，并且被布置在相同的硅衬底上，并且分别集成到 主电路和从电路。 每个谐振器元件与在谐振和反谐振频率附近设置的第一感应对象元件相关联; 并且利用第二电容性伙伴元件，所述对方元件中的至少一个可通过所述电信号（V调谐）调节。 控制两个伙伴元素可以通过可调电容器，变容二极管或通过电感器，被动或主动，固定或可变的方式完成。

公开(公告)号：US20050156700A1

公开(公告)日：2005-07-21

申请号：US11079717

申请日：2005-03-15

申请人： James Chang

发明人： James Chang

IPC分类号： H01F17/00 ,  H01L23/522 ,  H01L27/02 ,  H01L27/08 ,  H03B5/12 ,  H03B5/36 ,  H03D7/16 ,  H03D7/18 ,  H03G1/00 ,  H03H11/12 ,  H03J1/00 ,  H03J3/04 ,  H03J3/08 ,  H03J3/18 ,  H03L7/10 ,  H03L7/23 ,  H04B1/26

CPC分类号： H03L7/23 ,  H01F17/0006 ,  H01F17/0013 ,  H01F2017/0053 ,  H01F2021/125 ,  H01L23/5227 ,  H01L27/0248 ,  H01L27/08 ,  H01L2924/0002 ,  H01L2924/3011 ,  H03B5/364 ,  H03D7/161 ,  H03D7/18 ,  H03G1/0029 ,  H03H11/1291 ,  H03J1/0075 ,  H03J3/04 ,  H03J3/08 ,  H03J3/185 ,  H03J2200/10 ,  H03L7/10 ,  H01L2924/00

摘要： An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programable attenuation and a programable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors with shields to increase circuit Q. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator. The VCOs in the PLLs are centered using a control circuit to center the tuning capacitance range. A differential crystal oscillator is advantageously used as a frequency reference. Differential signal transmission is advantageously used throughout the receiver. ESD protection is provided by a pad ring and ESD clamping structure that maintains signal integrity. Also provided are shunts at each pin to discharge ESD build up. The shunts utilize a gate boosting structure to provide sufficient small signal RF performance, and minimal parasitic loading.

摘要翻译： 描述了基本上在单个CMOS集成电路上实现的具有信道选择和图像抑制的集成接收机。 接收机前端提供可编程衰减和可编程增益低噪声放大器。 频率转换电路有利地使用集成到衬底上的LC滤波器与图像抑制混合器结合，以提供足够的图像频率抑制。 过滤器调谐和电感Q补偿温度在芯片上执行。 滤波器利用具有屏蔽的多轨螺旋电感器来增加电路Q.使用本地振荡器调谐滤波器以调整替代滤波器，以及在滤波器组件值期间频率缩放至正被调谐的滤波器的滤波器。 结合滤波，频率规划提供了额外的镜像抑制。 片上本地振荡器信号产生方法的有利选择是通过PLL带外本地振荡和通过频带本地振荡器的直接合成。 PLL中的VCO使用控制电路居中，使调谐电容范围居中。 差分晶体振荡器有利地用作频率参考。 差分信号传输有利地用于整个接收机。 ESD保护由保护信号完整性的焊盘环和ESD钳位结构提供。 还提供每个引脚上的分流器，以放电ESD积聚。 分流器利用栅极升压结构来提供足够的小信号RF性能和最小的寄生负载。

公开(公告)号：US20050113051A1

公开(公告)日：2005-05-26

申请号：US10991072

申请日：2004-11-17

申请人： Masaki Yamamoto

发明人： Masaki Yamamoto

IPC分类号： H03J3/18 ,  H03J3/28 ,  H03J5/24 ,  H04B1/18 ,  H04N5/44

CPC分类号： H04N5/4446 ,  H03J3/185 ,  H03J5/244

摘要： A band switchable type tuning circuit has first switch mean interposed between a power supply Vcc and an anode of a switch diode, a first resistor whose one end is connected to a cathode of the switch diode, second switch means interposed between the other end of the first resistor and a ground, a second resistor connected between the power supply Vcc and a connection point of the first resistor and the second switch means, and the third resistor connected between the ground and a connection point of the first switch means and the anode of the switch diode. The first switch means and the second switch means are turned on or off together by means of a band switching voltage.

摘要翻译： 频带切换型调谐电路具有介于电源Vcc和开关二极管的阳极之间的第一开关平面，其一端连接到开关二极管的阴极的第一电阻器，插入在开关二极管的另一端之间的第二开关装置 第一电阻器和地，连接在电源Vcc与第一电阻器和第二开关装置的连接点之间的第二电阻器，以及连接在地与第一开关装置和阳极的连接点之间的第三电阻器 开关二极管。 第一开关装置和第二开关装置通过带开关电压一起接通或断开。

公开(公告)号：US20050083154A1

公开(公告)日：2005-04-21

申请号：US10494655

申请日：2002-11-12

申请人： Hiroshi Miyagi

发明人： Hiroshi Miyagi

IPC分类号： H03J1/00 ,  H03J3/18 ,  H03J3/20 ,  H03J3/06

CPC分类号： H03J3/20 ,  H03J1/0033 ,  H03J3/185

摘要： A receiver capable of reducing the number of pads of a semiconductor device used for connection with a tuning circuit. The receiver includes a semiconductor device 100 containing various circuits and a tuning circuit 130 connected as a separate part to this semiconductor device 100. The semiconductor device 100 has a pad 112 formed on a semiconductor substrate 110, a processing circuit 114 connected via a capacitor 120 to the pad 112, and aD/A converter 122 connected via a resistor 124 to the pad 112. A tuning voltage generated by the D/A converter 122 is applied via the pad 112 to the tuning circuit 130. Moreover, an output signal of the tuning circuit 130 is supplied to the pad 112 and fed via the capacitor 120 to the processing circuit 114.

摘要翻译： 一种能够减少用于与调谐电路连接的半导体器件的焊盘数量的接收器。 接收机包括：包含各种电路的半导体器件100和作为该半导体器件100的单独部分连接的调谐电路130。 半导体器件100具有形成在半导体衬底110上的焊盘112，经由电容器120连接到焊盘112的处理电路114以及经由电阻器124连接到焊盘112的D / A转换器122。 由D / A转换器122产生的调谐电压通过焊盘112施加到调谐电路130。 此外，调谐电路130的输出信号被提供给焊盘112，并经由电容器120馈送到处理电路114。