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公开(公告)号：US11923711B2
公开(公告)日：2024-03-05
申请号：US17501090
申请日：2021-10-14
申请人： AMOGY Inc.
发明人： Maxwell Spencer Mann
CPC分类号： H02J7/0068 , H02J7/0048 , H03F3/45475 , H03K3/86
摘要： A system comprises a positive voltage supply node and a negative voltage supply node configured for connection to a load, a power source coupled between the positive voltage supply node and the negative voltage supply node, an energy storage device, a solid-state switch, and a control system. The energy storage device and the solid-state switch are connected in series between the positive voltage supply node and the negative voltage supply node. The control system is configured to control activation and deactivation of the solid-state switch to (i) allow the energy storage device to be discharged and supply power to a load, and to (ii) modulate an amount of charging current that flows through the energy storage device from the power source (or load) to recharge the energy storage device.
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公开(公告)号：US11703905B1
公开(公告)日：2023-07-18
申请号：US17866682
申请日：2022-07-18
发明人： Jianyong Qin , Jianni Li , Zhonglai Liu
IPC分类号： G06F1/06 , H03K3/86 , H03K5/06 , H03K19/1776 , H03K5/05
CPC分类号： G06F1/06 , H03K3/86 , H03K5/05 , H03K5/06 , H03K19/1776
摘要： A clock generation circuit, equidistant four-phase signal generation method and memory are provided. The circuit includes: a four-phase clock generation circuit for receiving an internal clock signal and complementary clock signal of a memory to which the clock generation circuit belongs, configured to generate a first, second, third and fourth clock signals with the same cycle; a signal delay circuit configured to perform signal delay on the first clock signal, second clock signal, third clock signal and fourth clock signal respectively based on the delay command, herein the delays of the first clock signal, second clock signal, third clock signal and fourth clock signal are different; a signal loading circuit configured to generate a first indication signal and second indication signal; and a test circuit configured to perform a duty cycle test based on the first indication signal and second indication signal to acquire equidistant parallel clock signals.
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公开(公告)号：US10705738B2
公开(公告)日：2020-07-07
申请号：US16035703
申请日：2018-07-15
发明人： Jinsuo Yu , Xuewu Zhang
摘要： Embodiments of the disclosure provide a method, apparatus, and computer readable medium for optimizing memory card performance. The method includes: determining a plurality of different preset time intervals, the preset time intervals being determined beginning from clock-cycle starting points; sending test data to a memory card using each of the preset time intervals, respectively; reading from the memory card the test data corresponding to each of the preset time intervals; comparing the test data sent using each of the preset time intervals with the corresponding test data that is read; in response to the sent test data and the read test data being consistent, determining that the preset time interval is valid; determining at least one group of preset time intervals, each of the groups of preset time intervals containing a plurality of valid and successive preset time intervals; determining a group of preset time intervals containing a maximum number of preset time intervals as a target group; determining an average value of all the preset time intervals in the target group as a time interval for writing to the memory card.
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4.发明授权公开(公告)号：US09503064B2
公开(公告)日：2016-11-22
申请号：US14792985
申请日：2015-07-07
发明人： Gyeonghan Cha , Han-Kyul Lim , SungJun Kim , Chaeryung Kim , DongUk Park , Younwoong Chung , JungMyung Choi
摘要： A skew calibration circuit may include a data delay unit receiving first data and a first code, and output delayed first data as second data by delaying the first data according to the first code; a clock delay unit receiving a first clock signal and a second code, and output delayed first clock signal as second clock signal by delaying the first clock signal according to the second code; a multiplexer receiving a clock signal and output the clock signal or an inverted clock signal of the clock signal as a first clock signal in response to a selection signal; and a control logic unit receiving the second data and the second clock signal and control the first code, the second code and the selection signal in response to the second data and the second clock signal.
摘要翻译： 偏斜校准电路可以包括接收第一数据和第一代码的数据延迟单元，并且通过根据第一代码延迟第一数据来将延迟的第一数据作为第二数据输出; 时钟延迟单元，接收第一时钟信号和第二代码，并且通过根据第二代码延迟第一时钟信号，将延迟的第一时钟信号作为第二时钟信号输出; 多路复用器响应于选择信号，接收时钟信号并输出时钟信号或时钟信号的反相时钟信号作为第一时钟信号; 以及控制逻辑单元，其接收第二数据和第二时钟信号，并且响应于第二数据和第二时钟信号来控制第一代码，第二代码和选择信号。
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公开(公告)号：US09356585B2
公开(公告)日：2016-05-31
申请号：US13711414
申请日：2012-12-11
发明人： Katsuhito Sakurai , Itsutaku Sano
CPC分类号： H03K3/86 , H01L27/14603 , H01L27/14609 , H01L27/1464 , H03K4/026 , H03K5/2472 , H04N5/378
摘要： An electronic device according to one or more embodiments of the present invention comprises an output line, a current mirror circuit and a comparator. Current signals from a plurality of signal sources are output to the output line. The current mirror circuit is electrically connected to the output line. The comparator is configured to compare a mirrored current signal from the current mirror circuit with a reference current signal. The comparator is configured to output a signal representing a comparison result of amplitudes of the mirrored current signal and the reference current signal.
摘要翻译： 根据本发明的一个或多个实施例的电子设备包括输出线，电流镜电路和比较器。 来自多个信号源的电流信号被输出到输出线。 电流镜电路电连接到输出线。 比较器被配置为将来自电流镜像电路的镜像电流信号与参考电流信号进行比较。 比较器被配置为输出表示镜像电流信号和参考电流信号的幅度的比较结果的信号。
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6.发明申请SKEW CALIBRATION CIRCUIT AND OPERATION METHOD OF THE SKEW CALIBRATION CIRCUIT 有权SKEW校准电路和SKEW校准电路的操作方法公开(公告)号：US20160036420A1
公开(公告)日：2016-02-04
申请号：US14792985
申请日：2015-07-07
发明人： Gyeonghan CHA , Han-Kyul LIM , SungJun KIM , Chaeryung KIM , DongUk PARK , Younwoong CHUNG , JungMyung CHOI
IPC分类号： H03K3/86
摘要： A skew calibration circuit may include a data delay unit receiving first data and a first code, and output delayed first data as second data by delaying the first data according to the first code; a clock delay unit receiving a first clock signal and a second code, and output delayed first clock signal as second clock signal by delaying the first clock signal according to the second code; a multiplexer receiving a clock signal and output the clock signal or an inverted clock signal of the clock signal as a first clock signal in response to a selection signal; and a control logic unit receiving the second data and the second clock signal and control the first code, the second code and the selection signal in response to the second data and the second clock signal.
摘要翻译： 偏斜校准电路可以包括接收第一数据和第一代码的数据延迟单元，并且通过根据第一代码延迟第一数据来将延迟的第一数据作为第二数据输出; 时钟延迟单元，接收第一时钟信号和第二代码，并且通过根据第二代码延迟第一时钟信号，将延迟的第一时钟信号作为第二时钟信号输出; 多路复用器响应于选择信号，接收时钟信号并输出时钟信号或时钟信号的反相时钟信号作为第一时钟信号; 以及控制逻辑单元，其接收第二数据和第二时钟信号，并且响应于第二数据和第二时钟信号来控制第一代码，第二代码和选择信号。
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7.发明申请SEMICONDUCTOR DEVICE, SEMICONDUCTOR SYSTEM AND METHOD FOR OPERATING SEMICONDUCTOR DEVICE 有权半导体器件，半导体器件和半导体器件操作方法公开(公告)号：US20150333759A1
公开(公告)日：2015-11-19
申请号：US14489157
申请日：2014-09-17
申请人： SK hynix Inc.
发明人： Ji-Wan JUNG
CPC分类号： H03L7/0802 , G06F1/08 , G06F1/324 , G06F1/3296 , G11C7/222 , G11C29/023 , G11C29/028 , H03K3/86 , H03L7/0805 , H03L7/0814 , H03L7/0816 , H03L7/083 , H03L7/10
摘要： A semiconductor device includes a code generation block configured to generate an output clock by delaying a reference clock which is inputted from an exterior, control a delay value of the output clock based on a result of comparing phases of the reference clock and a feedback clock, and generate a first control code corresponding to the delay value of the output clock, a voltage generation block configured to generate an internal voltage with a voltage level corresponding to the first control code, a clock generation block configured to generate an internal clock with a frequency corresponding to the first control code, and a feedback delay block configured to generate the feedback clock by delaying the output clock by a delay value corresponding to a second control code.
摘要翻译： 一种半导体器件，包括代码生成块，其被配置为通过延迟从外部输入的参考时钟来生成输出时钟，基于比较参考时钟的相位和反馈时钟的结果来控制输出时钟的延迟值， 并产生与输出时钟的延迟值相对应的第一控制代码，电压产生块，被配置为产生具有与第一控制代码相对应的电压电平的内部电压;时钟产生模块，用于产生具有频率的内部时钟 以及反馈延迟块，被配置为通过将输出时钟延迟与第二控制码对应的延迟值来产生反馈时钟。
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公开(公告)号：US20140084140A1
公开(公告)日：2014-03-27
申请号：US14030225
申请日：2013-09-18
申请人： OLYMPUS CORPORATION
发明人： Yosuke Kusano
IPC分类号： H03K3/86 , H01L27/146
CPC分类号： H03K3/86 , H01L27/14601 , H04N5/378
摘要： A data processing circuit that holds a state of a clock signal of each phase of an input multi-phase clock at a timing of an input latch clock, the multi-phase clock including clock signals of a plurality of phases sequentially shifted at certain intervals determined in advance, and generates a digital signal obtained by digitizing the states of the phases of the multi-phase clock at a timing at which the latch clock is input, the data processing circuit including: a latch portion including n latch unit groups (n is an integer of a power of 2) including the same number and a plurality of latch units, each latch unit holding the state of the clock signal of the corresponding phase of the multi-phase clock and outputting an output signal indicating the held state of the clock signal.
摘要翻译： 一种数据处理电路，其在输入锁存时钟的定时保持输入多相时钟的各相的时钟信号的状态，所述多相时钟包括以确定的一定间隔顺序移位的多个相的时钟信号 并且产生通过在输入锁存时钟的定时数字化多相时钟的相位状态而获得的数字信号，所述数据处理电路包括：锁存部分，包括n个锁存单元组（n是 每个锁存单元保持多相时钟的相应相位的时钟信号的状态，并输出指示该多相时钟的保持状态的输出信号， 时钟信号。
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9.发明申请SIGNAL DELAY CIRCUIT, CLOCK TRANSFER CONTROL CIRCUIT AND SEMICONDUCTOR DEVICE HAVING THE SAME 有权信号延迟电路，时钟传输控制电路和具有该信号的半导体器件公开(公告)号：US20120280737A1
公开(公告)日：2012-11-08
申请号：US13552037
申请日：2012-07-18
申请人： Hyoung-Jun NA , Kyung-Whan KIM
发明人： Hyoung-Jun NA , Kyung-Whan KIM
IPC分类号： H03K3/86
CPC分类号： H03K5/04
摘要： A signal delay circuit including a clock transfer control circuit configured to transmit or block a clock signal, and a pulse signal generation circuit configured to delay a first pulse signal in response to the transmitted clock signal to generate a second pulse signal which has a longer active period than the first pulse signal.
摘要翻译： 一种信号延迟电路，包括被配置为发送或阻断时钟信号的时钟传送控制电路，以及脉冲信号生成电路，被配置为响应于发送的时钟信号而延迟第一脉冲信号，以产生具有较长活动的第二脉冲信号 周期比第一脉冲信号。
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公开(公告)号：US08212418B2
公开(公告)日：2012-07-03
申请号：US13185896
申请日：2011-07-19
申请人： Simon London
发明人： Simon London
摘要： A bipolar pulse generator is implemented in a simple structure while providing a high efficiency design having a relatively low total size, while still allowing access by fibers used to control a photoconductive switch that activates the generator. The bipolar pulse generator includes a stacked Blumlein generator structure with an additional transmission line connected to a load at its near end and short-circuited at its distal end. An extra transmission line is positioned between the Blumlein generator's structure and the load provides specified limited gap between positive and negative sub-pulses. The bipolar pulse generator further includes a bended Blumlein generator structure, in which an existing intrinsic “stray” transmission line is used to provide the bipolar pulse. Still further, bipolar pulse generator includes stepped transmission lines, with additional switches positioned between steps, which are charged by different voltages.
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