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公开(公告)号:US20240305331A1
公开(公告)日:2024-09-12
申请号:US18581635
申请日:2024-02-20
发明人: Hyun Jun PARK , Woo-Seok CHOI
CPC分类号: H04B3/32 , H04L25/085 , H04L25/4923
摘要: A communication system includes a transmitter that encodes binary bits of each of a plurality of data streams into a plurality of symbols and converts the plurality of symbols into a plurality of output signals, respectively corresponding to a plurality of channels, the converting based on a transmission rule defined by a first matrix; and a receiver that combines the plurality of output signals, received through the plurality of channels, the combining based on a reception rule defined by a second matrix, the combining restoring the plurality of symbols, and the receiver decodes the plurality of symbols into the binary bits. The first matrix and the second matrix are determined based on a third matrix that models a crosstalk effect between adjacent channels from among the plurality of channels, to reduce the crosstalk effect.
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公开(公告)号:US20240267266A1
公开(公告)日:2024-08-08
申请号:US18402279
申请日:2024-01-02
发明人: Fa-Long Luo , Jeremy Chritz , Jaime Cummins , Tamara Schmitz
IPC分类号: H04L25/08 , H04B1/10 , H04B1/12 , H04B1/525 , H04B7/04 , H04B17/21 , H04B17/345 , H04L5/00 , H04L5/14 , H04L25/02 , H04L25/03 , H04L27/26
CPC分类号: H04L25/08 , H04B1/10 , H04B1/123 , H04B1/525 , H04B17/21 , H04B17/345 , H04L5/0023 , H04L5/14 , H04L25/0224 , H04L25/03866 , H04L27/2601 , H04B7/04
摘要: Examples described herein include systems and methods which include wireless devices and systems with examples of full duplex compensation with a self-interference noise calculator. The self-interference noise calculator may be coupled to antennas of a wireless device and configured to generate adjusted signals that compensate self-interference. The self-interference noise calculator may include a network of processing elements configured to combine transmission signals into sets of intermediate results. Each set of intermediate results may be summed in the self-interference noise calculator to generate a corresponding adjusted signal. The adjusted signal is received by a corresponding wireless receiver to compensate for the self-interference noise generated by a wireless transmitter transmitting on the same frequency band as the wireless receiver is receiving.
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公开(公告)号:US20240235728A1
公开(公告)日:2024-07-11
申请号:US18416434
申请日:2024-01-18
申请人: Kandou Labs, S.A.
发明人: Amin Shokrollahi , Ali Hormati
IPC分类号: H04L1/00 , H03M13/00 , H03M13/05 , H03M13/15 , H03M13/27 , H03M13/37 , H04J13/00 , H04L25/02 , H04L25/08
CPC分类号: H04L1/0041 , H03M13/05 , H03M13/1515 , H03M13/27 , H03M13/3761 , H03M13/6561 , H04J13/004 , H04L1/0071 , H04L25/0272 , H04L25/085
摘要: Methods and systems are described for obtaining a plurality of information bits, and responsively partitioning the obtained plurality of information bits into a plurality of subsets of information bits, generating a plurality of streams of forward error correction (FEC)-encoded bits using a plurality of FEC encoders receiving respective subsets of the plurality of subsets of information bits, providing the plurality of streams of FEC-encoded bits to a plurality of sub-channel encoders, each sub-channel encoder receiving a respective stream of FEC-encoded bits from a different FEC encoder of the plurality of FEC encoders for generating a set of codewords of a vector signaling code, and wherein sequential streams of FEC-encoded bits from a given FEC encoder are provided to different sub-channel encoders for each successively generated set of codewords, and transmitting the successively generated sets of codewords of the vector signaling code over a multi-wire bus.
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公开(公告)号:US20240219952A1
公开(公告)日:2024-07-04
申请号:US18601440
申请日:2024-03-11
申请人: KIOXIA CORPORATION
发明人: Toshitada SAITO , Akihisa FUJIMOTO
IPC分类号: G06F1/06 , G06F1/12 , G06F13/38 , G06F13/42 , H03L7/00 , H03L7/07 , H03L7/08 , H03L7/091 , H03L7/099 , H04L7/00 , H04L7/033 , H04L25/08 , H04L25/14
CPC分类号: G06F1/06 , G06F1/12 , G06F13/38 , G06F13/4282 , H03L7/00 , H03L7/07 , H03L7/0807 , H03L7/091 , H03L7/099 , H04L7/0004 , H04L7/033 , H04L25/085 , H04L25/14 , H04L7/0012
摘要: According to one embodiment, an interface system includes a receiver, a first clock generator, a second clock generator, and a sampling circuit. The receiver is configured to receive a first clock and serial data from a host. The first clock generator includes a first voltage controlled oscillator (VCO) and is configured to generate a second clock on the basis of the first clock. The second clock generator includes a second voltage controlled oscillator (VCO) and is configured to generate a third clock on the basis of the serial data. The sampling circuit is configured to sample reception data on the basis of the third clock and the serial data.
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公开(公告)号:US20240121138A1
公开(公告)日:2024-04-11
申请号:US18263278
申请日:2022-02-03
IPC分类号: H04L25/02 , H04B1/3822 , H04B1/56 , H04B1/58 , H04L25/08
CPC分类号: H04L25/0276 , H04B1/3822 , H04B1/56 , H04B1/581 , H04L25/085 , H04L2012/40215
摘要: An electronic control device includes: a first input-output terminal and a second input-output terminal through which differential signals are input and output; a transceiver integrated circuit (IC) that transmits and receives the differential signals; a first line that connects the first input-output terminal and the transceiver IC; and a second line that connects the second input-output terminal and the transceiver IC. A first capacitance that is a capacitance between the first line and a ground is at least 80 pF and at most 220 pF, and a second capacitance that is a capacitance between the second line and the ground is at least 80 pF and at most 220 pF.
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公开(公告)号:US11949540B2
公开(公告)日:2024-04-02
申请号:US17803636
申请日:2022-09-12
申请人: Brian G. Agee
发明人: Brian G. Agee
CPC分类号: H04L25/08 , H04B7/0617 , H04L27/264 , H04L27/26414 , H04L27/26538 , H04W28/14 , H04W52/52
摘要: An apparatus and digital signal processing means are disclosed for excision of co-channel interference from signals received in crowded or hostile environments using spatial/polarization diverse arrays, which reliably and rapidly identifies communication signals with transmitted features that are self-coherent over known framing intervals due to known attributes of the communication network, and exploits those features to develop diversity combining weights that substantively excise that co-channel interference from those communication signals, based on differing diversity signature, timing offset, and carrier offset between the network signals and the co-channel interferers. In one embodiment, the co-channel interference excision is performed in an appliqué that can be implemented without coordination with a network transceiver.
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公开(公告)号:US11831366B2
公开(公告)日:2023-11-28
申请号:US18187505
申请日:2023-03-21
发明人: Harm Cronie , Amin Shokrollahi
CPC分类号: H04B7/0413 , H04B10/54 , H04L5/0007 , H04L25/0272 , H04L25/085 , H04L25/4906
摘要: Using a transformation based at least in part on a non-simple orthogonal or unitary matrix, data may be transmitted over a data bus in a manner that is resilient to one or more types of signal noise, that does not require a common reference at the transmission and acquisition points, and/or that has a pin-efficiency that is greater than 50% and may approach that of single-ended signaling. Such transformations may be implemented in hardware in an efficient manner. Hybrid transformers that apply such transformations to selected subsets of signals to be transmitted may be used to adapt to various signal set sizes and/or transmission environment properties including noise and physical space requirements of given transmission environments.
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公开(公告)号:US20230269122A1
公开(公告)日:2023-08-24
申请号:US18010152
申请日:2020-06-15
发明人: Juejia ZHOU
CPC分类号: H04L27/2649 , H04L25/08
摘要: A method for determining a vortex wave phase offset is performed by an access network device. The method includes: determining vortex wave phase offsets used by adjacent access network devices, so as to obtain a first set of vortex wave phase offsets; and determining a target vortex wave phase offset according to the first set of vortex wave phase offsets and a pre-configured set of available vortex wave phase offsets.
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公开(公告)号:US20230251682A1
公开(公告)日:2023-08-10
申请号:US18301669
申请日:2023-04-17
申请人: KIOXIA CORPORATION
发明人: Toshitada SAITO , Akihisa FUJIMOTO
IPC分类号: G06F1/06 , H04L7/00 , H04L7/033 , H03L7/07 , H03L7/091 , H03L7/00 , H04L25/08 , H04L25/14 , G06F1/12 , G06F13/38 , G06F13/42 , H03L7/08 , H03L7/099
CPC分类号: G06F1/06 , H04L7/0004 , H04L7/033 , H03L7/07 , H03L7/091 , H03L7/00 , H04L25/085 , H04L25/14 , G06F1/12 , G06F13/38 , G06F13/4282 , H03L7/0807 , H03L7/099 , H04L7/0012
摘要: According to one embodiment, an interface system includes a receiver, a first clock generator, a second clock generator, and a sampling circuit. The receiver is configured to receive a first clock and serial data from a host. The first clock generator includes a first voltage controlled oscillator (VCO) and is configured to generate a second clock on the basis of the first clock. The second clock generator includes a second voltage controlled oscillator (VCO) and is configured to generate a third clock on the basis of the serial data. The sampling circuit is configured to sample reception data on the basis of the third clock and the serial data.
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公开(公告)号:US20230071030A1
公开(公告)日:2023-03-09
申请号:US18047610
申请日:2022-10-18
申请人: Kandou Labs, S.A.
发明人: Ali Hormati
摘要: Methods and systems are described for receiving symbols of a codeword via wires of a multi-wire bus, the codeword representing an aggregate sum of a plurality of sub-channel constituent codewords, each sub-channel constituent codeword representing a weight applied to an associated sub-channel vector of a plurality of sub-channel vectors of an orthogonal matrix, generating a plurality of comparator outputs using a plurality of common-mode resistant multi-input comparators (MICs), each common-mode resistant MIC having a set of input coefficients representing a corresponding sub-channel vector of the plurality of sub-channel vectors, each sub-channel vector (i) mutually orthogonal and (ii) orthogonal to a common-mode sub-channel vector, outputting a set of forward-channel output bits formed based on the plurality of comparator outputs, obtaining a sequence of reverse-channel bits, and transmitting the sequence of reverse-channel bits by sequentially transmitting common-mode codewords over the wires of the multi-wire bus.
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