公开(公告)号：WO2008140661A1

公开(公告)日：2008-11-20

申请号：PCT/US2008/004667

申请日：2008-04-10

Applicant: SPANSION LLC ,  DING, Meng ,  SUH, YouSeok ,  FANG, Shenqing ,  CHANG, Kuo-Tung

Inventor： DING, Meng ,  SUH, YouSeok ,  FANG, Shenqing ,  CHANG, Kuo-Tung

IPC: H01L21/28 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L23/528 ,  H01L27/02

CPC classification number: H01L29/788 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/762 ,  H01L21/76224 ,  H01L27/0207 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/792

Abstract: An embodiment of the present invention is directed to a method of forming a memory cell. The method includes etching a trench in a substrate and filling the trench with an oxide to form a shallow trench isolation (STI) region. A portion of an actxve region of the substrate that comes in contact with the STI region forms a bitline-STI edge. The method further includes forming a gate structure over the active region of the substrate and over the STI region. The gate structure has a first width substantially over the center of the active region of the substrate and a second width substantially over the bitline-STI edge, and the second width is greater than the first width. An electrical current (330) flows along the bitlines (310) that are covered by wordlines (320).

Abstract translation: 本发明的实施例涉及一种形成存储单元的方法。 该方法包括蚀刻衬底中的沟槽并用氧化物填充沟槽以形成浅沟槽隔离（STI）区域。 与STI区域接触的衬底的actxve区域的一部分形成位线STI边缘。 该方法还包括在衬底的有源区上方和STI区上方形成栅极结构。 栅极结构具有基本上在衬底的有源区域的中心上方的第一宽度和基本上位于STI边缘的第二宽度，并且第二宽度大于第一宽度。 电流（330）沿着由字线（320）覆盖的位线（310）流动。

公开(公告)号：WO2008097779A1

公开(公告)日：2008-08-14

申请号：PCT/US2008/052477

申请日：2008-01-30

Applicant: MAXIM INTEGRATED PRODUCTS, INC. ,  BERGEMONT, Albert ,  LIU, David, Kuan-yu ,  PRABHAKAR, Venkatraman

Inventor： BERGEMONT, Albert ,  LIU, David, Kuan-yu ,  PRABHAKAR, Venkatraman

IPC: H01L29/788 ,  H01L29/423

CPC classification number: H01L29/7885 ,  G11C16/0416 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42324

Abstract: Methods and apparatus, including computer program products, for a one or multiple- times programmable memory device. A semiconductor may include an active region of a substrate, a thin oxide layer over a substrate, a first and second polysilicon layer, and a first and second metal layer. The first polysilicon layer may have a floating gate, the active region may be substantially perpendicular to the floating gate, and the second polysilicon layer may include a control gate. The first metal layer may include a bit line connected to a first n-diffused region, where the bit line is substantially perpendicular to the floating gate. The second metal layer may include a word line and source line. The word line may be connected to the control gate, and the source line may be connected to a second n-diffused region. The thin gate oxide may have a thickness between 65 and 75 angstroms.

Abstract translation: 用于一个或多个可编程存储器件的方法和装置，包括计算机程序产品。 半导体可以包括衬底的有源区，衬底上的薄氧化物层，第一和第二多晶硅层以及第一和第二金属层。 第一多晶硅层可以具有浮置栅极，有源区可以基本上垂直于浮置栅极，并且第二多晶硅层可以包括控制栅极。 第一金属层可以包括连接到第一n扩散区域的位线，其中位线基本上垂直于浮动栅极。 第二金属层可以包括字线和源极线。 字线可以连接到控制栅极，并且源极线可以连接到第二n扩散区域。 薄栅氧化物可以具有65和75埃之间的厚度。

公开(公告)号：WO2007089558A2

公开(公告)日：2007-08-09

申请号：PCT/US2007/002118

申请日：2007-01-25

Applicant: MONOLITHIC SYSTEM TECHNOLOGY, INC.

Inventor： FANG, Gang-feng ,  SINITSKY, Dennis ,  LEUNG, Wingyu

IPC: H01L29/76

CPC classification number: H01L29/7883 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42324

Abstract: A non-volatile memory cell with increased charge retention is fabricated on the same substrate as logic devices using single-gate conventional logic process. A silicide-blocking dielectric structure is formed over a floating gate of the NVM cell, thereby preventing silicide formation over the floating gate, while allowing silicide formation over the logic devices. Silicide spiking and bridging are prevented in the NVM cell, as silicide-blocking dielectric structure prevents silicide metal from coming in contact with the floating gate or adjacent sidewall spacers. The silicide-blocking dielectric layer may expose portions of the active regions of the NVM cell, away from the floating gate and adjacent sidewall spacers, thereby enabling silicide formation on these portions. Alternately, the silicide-blocking dielectric layer may cover the active regions of the NVM cell during silicide formation. In this case, silicide-blocking dielectric layer may be thinned or removed after silicide formation.

Abstract translation: 具有增加的电荷保持的非易失性存储单元在与使用单栅极常规逻辑工艺的逻辑器件相同的衬底上制造。 在NVM单元的浮动栅极上形成硅化物阻挡电介质结构，从而防止在浮栅上形成硅化物，同时允许在逻辑器件上形成硅化物。 在NVM电池中防止硅化物尖峰和桥接，因为硅化物阻挡电介质结构防止硅化物金属与浮动栅极或相邻的侧壁间隔物接触。 硅化物阻挡电介质层可以暴露NVM电池的有源区的部分，远离浮动栅极和相邻的侧壁间隔物，从而使得这些部分上形成硅化物。 或者，硅化物阻挡电介质层可以在硅化物形成期间覆盖NVM电池的有源区。 在这种情况下，硅化物阻挡介电层可以在形成硅化物之后变薄或去除。

公开(公告)号：WO2006007367A1

公开(公告)日：2006-01-19

申请号：PCT/US2005/021111

申请日：2005-06-16

Applicant: ATMEL CORPORATION

Inventor： LOJEK, Bohumil

IPC: H01L21/3205

CPC classification number: H01L27/115 ,  H01L21/28273 ,  H01L27/11519 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7883 ,  H01L29/7887

Abstract: By arranging floating spacer and gate non­volatile memory transistors (Fig. 1) in symmetric (30) pairs, increased chip density may be attained. For each pair of such transistors, the floating gates (17a, 17b) are laterally aligned with floating spacers (45, 47) appearing on laterally outward edges of each floating gate. At laterally inward edges, the two transistors share a common electrode (57). The transistors are independent of each other except for the shared electrode. Tunnel oxide (41) separated the floating spacer from the floating gate, but both the spacer and the gate are maintained at a common potential, thereby providing dual paths for charge exiting the tunnel oxide, as the charged is propelled by a programming voltage. The pairs of transistors can be aligned in columns with the direction of the columns orthogonal to the direction of the pairs, thereby forming a memory array.

Abstract translation: 通过将浮动间隔物和栅极非易失性存储晶体管（图1）布置在对称（30）对中，可以获得增加的芯片密度。 对于每对这样的晶体管，浮动栅极（17a，17b）与出现在每个浮动栅极的横向外边缘上的浮动间隔物（45,47）横向对准。 在横向内侧边缘处，两个晶体管共享公共电极（57）。 除共享电极之外，晶体管彼此独立。 隧道氧化物（41）将浮动隔离物与浮动栅极分离，但是间隔物和栅极都保持在公共电位，从而为通过编程电压驱动的电荷提供了离开隧道氧化物的电荷的双路径。 可以使列对中的列对齐，其中列的方向与对的方向正交，从而形成存储器阵列。

公开(公告)号：WO2005074471A2

公开(公告)日：2005-08-18

申请号：PCT/US2004/043197

申请日：2004-12-21

Applicant: FREESCALE SEMICONDUCTOR, INC.? ,  INGERSOLL, Paul, A. ,  CHINDALORE, Gowrishankar, L. ,  MURALIDHAR, Ramachandran

Inventor： INGERSOLL, Paul, A. ,  CHINDALORE, Gowrishankar, L. ,  MURALIDHAR, Ramachandran

IPC: C09K17/14 ,  C09K17/40 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/16 ,  H01L29/423

CPC classification number: H01L29/42324 ,  B82Y10/00 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/4925 ,  H01L29/4958

Abstract: To increase the gate coupling ratio of a semiconductor device 10, discrete elements 22, such as nanocrystals, are deposited over a floating gate 16. In one embodiment, the discrete elements 22 are pre-formed in a vapor phase and are attached to the semiconductor device 10 by electrostatic force. In one embodiment, the discrete elements 22 are pre-formed in a different chamber than that where they are attached. In another embodiment, the same chamber is used for the entire deposition process. An optional, interfacial layer 17 may be formed between the floating gate 16and the discrete elements 22.

Abstract translation: 为了增加半导体器件10的栅极耦合比率，在浮动栅极16上沉积诸如纳米晶体的分立元件22.在一个实施例中，分立元件22预先形成为 气相并通过静电力附着到半导体器件10。 在一个实施例中，分离元件22预先形成在与其附着的不同的腔室中。 在另一个实施例中，整个沉积过程使用相同的腔室。 可选的界面层17可以形成在浮栅16和离散元件22之间。

公开(公告)号：WO2005013373A1

公开(公告)日：2005-02-10

申请号：PCT/US2004/023531

申请日：2004-07-21

Applicant: ATMEL CORPORATION

Inventor： LOJEK, Bohumil

IPC: H01L29/76

CPC classification number: H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11558 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7881

Abstract: An EEPROM device constructed in a first active area (21) having a multi-element floating gate structure, including a central polysilicon body (51) surrounded by a polysilicon spacer element (69) and mutually separated by an upright layer (63) of thin oxide (61) for electron tunneling. An auxiliary active area (23), isolated from the first active area, is employed as a charge reservoir for programming and linked to the first active area by an extended ion implantation region (45). A poly cap (99) makes contact with the poly spacer (69) but not the central poly body (51). A hole (82), made through the poly cap and into the central poly body, is then filled with metal (91), electrically joining the poly cap and the connected poly spacer with the central poly body.

Abstract translation: 一种EEPROM器件，其构造在具有多元件浮置栅极结构的第一有源区域（21）中，包括由多晶硅间隔元件（69）围绕并由薄的直立层（63）相互分隔的中心多晶硅体（51） 氧化物（61）用于电子隧穿。 采用与第一有源区隔离的辅助有源区（23）作为用于编程的电荷储存器，并通过延伸的离子注入区（45）与第一有源区连接。 聚盖（99）与聚间隔物（69）接触，而不与中心聚体（51）接触。 然后用金属（91）填充通过多晶硅帽制成并进入中心多晶体体的孔（82），将聚盖和电连接的聚间隔物与中心聚体电连接。

公开(公告)号：WO2005001840A2

公开(公告)日：2005-01-06

申请号：PCT/US2004015651

申请日：2004-05-18

Applicant: ATMEL CORP

Inventor： LOHEK BOHUMIL

IPC: G11C20060101 ,  G11C16/04 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/76 ,  H01L29/788 ,  H01L29/792 ,  G11C

CPC classification number: H01L21/28273 ,  G11C16/0416 ,  G11C2216/10 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11558 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7887

Abstract: An arrangement of non-volatile memory transistors (11, 13, 15; 21, 23, 25; 31, 33, 35; etc.) constructed in symmetric pairs (14, 30) within the space defined by intersecting pairs of word (WL; 22, 24) and bit (BL; 10, 20) lines of a memory array. The transistors have spaced apart sources (32) and drains (34) separated by a channel and having a floating gate (28; 40, 42) over the channel characteristic of electrically erasable programmable read only memory transistors, except that there is no second poly gate. Only a single poly gate is used as a floating charge storage gate, which is placed sufficiently close to the source or drain of the device as to enable band-to-band tunneling. The single layer of poly has a T-shape, with a T-base (42) used as a floating gate and a T-top (40) extending over a word line in capacitive relation therewith. The word line is used to program and erase the floating gate in combination with a source or drain electrode. A block erase mode is available so that the arrangement of transistors can operate as a flash memory.

Abstract translation: 在由相交字对（WL，WL）定义的空间内以对称对（14,30）构造的非易失性存储器晶体管（11,13,15; 21,23,25; 31,33,35等） ; 22,24）和存储器阵列的位（BL; 10,20）行。 晶体管具有由沟道隔开的间隔开的源极（32）和漏极（34），并且在电可擦除可编程只读存储器晶体管的沟道特性上具有浮置栅极（28; 40,42），除了不存在第二聚 门。 只有一个多晶栅极用作浮动电荷存储栅极，其被放置得足够靠近器件的源极或漏极以实现带间隧穿。 单层多晶硅具有T形形状，具有用作浮置栅极的T型底座（42）和在与之电容性关系的字线上延伸的T型顶部（40）。 字线用于编程和擦除与源极或漏极结合的浮动栅极。 块擦除模式是可用的，因此晶体管的布置可以作为闪存进行操作。

公开(公告)号：WO2004034468A9

公开(公告)日：2004-05-27

申请号：PCT/US0332119

申请日：2003-10-08

Applicant: SANDISK CORP

Inventor： YUAN JACK H

IPC: H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L27/00

CPC classification number: H01L27/11521 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11543 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7881

Abstract: Floating gate structures are disclosed which have a base field coupled with the substrate and a narrow projection extending from the base away from the substrate. In one form, surfaces of a relatively large projection provide an increased surface area for a control gate that wraps around it, thereby increasing the coupling between the two. In another form, an erase gate wraps around a relatively small projection in order to take advantage of sharp edges of the projection to promote tunneling of electrons from the floating to the erase gate. In each case, the control or floating gate is positioned within the area of the floating gate in one direction, thereby not requiring additional substrate area for such memory cells.

Abstract translation: 公开了浮动栅极结构，其具有与基底耦合的基极区域和从基底远离基底延伸的窄突起。 在一种形式中，相对大的突起的表面为包围其的控制栅提供增加的表面积，从而增加两者之间的耦合。 在另一种形式中，擦除栅极围绕相对较小的突起卷绕，以便利用突起的尖锐边缘来促进电子从浮动栅极到擦除栅极的隧穿。 在每种情况下，控制或浮动栅极在一个方向上位于浮动栅极的区域内，从而不需要这种存储器单元的附加衬底区域。

公开(公告)号：WO2004040658A1

公开(公告)日：2004-05-13

申请号：PCT/EP2003/050764

申请日：2003-10-28

Applicant: TOUMAZ TECHNOLOGY LIMITED ,  LANDE, Tor, Sverre

Inventor： LANDE, Tor, Sverre

IPC: H01L29/788

CPC classification number: H01L29/66825 ,  G06G7/60 ,  G11C27/005 ,  H01L21/28273 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/788

Abstract: A floating gate MOS transistor comprises one or more control gates, an active channel, and at least one floating gate disposed between the control gate(s) and the active channel. First and second non-linear resistances couple the floating gate to first and second control voltage sources respectively, the non-linear resistances forming a voltage divider network which sets the operating voltage of the floating gate.

Abstract translation: 浮置栅极MOS晶体管包括一个或多个控制栅极，有源沟道以及设置在控制栅极和有源沟道之间的至少一个浮置栅极。 第一和第二非线性电阻分别将浮动栅极耦合到第一和第二控制电压源，非线性电阻形成分压网络，其设置浮动栅极的工作电压。

公开(公告)号：WO2004015764A2

公开(公告)日：2004-02-19

申请号：PCT/US2003/025048

申请日：2003-08-08

Applicant: LEEDY, Glenn, J.

Inventor： LEEDY, Glenn, J.

IPC: H01L23/00

CPC classification number: H04W4/80 ,  B81B7/02 ,  B81C1/00238 ,  B81C1/00246 ,  B81C2203/0771 ,  G06F17/5068 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/8252 ,  H01L21/84 ,  H01L22/34 ,  H01L23/481 ,  H01L23/52 ,  H01L23/544 ,  H01L23/66 ,  H01L25/0657 ,  H01L25/18 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10805 ,  H01L27/115 ,  H01L27/118 ,  H01L27/11803 ,  H01L27/1203 ,  H01L27/1463 ,  H01L27/14643 ,  H01L27/14683 ,  H01L29/42324 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7827 ,  H01L29/7831 ,  H01L29/78648 ,  H01L29/7881 ,  H01L2223/54453 ,  H01L2223/6677 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2225/06596 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The Vertical System Integration (VSI) invention herein is a method for integration of disparate electronic, optical and MEMS technologies into a single integrated circuit die or component and wherein the individual device layers used in the VSI fabrication processes are preferably previously fabricated components intended for generic multiple application use and not necessarily limited in its use to a specific application. The VSI method of integration lowers the cost difference between lower volume custom electronic products and high volume generic use electronic products by eliminating or reducing circuit design, layout, tooling and fabrication costs.

Abstract translation: 本文中的垂直系统集成（VSI）发明是将不同的电子，光学和MEMS技术集成到单个集成电路管芯或部件中的方法，并且其中在VSI制造工艺中使用的各个器件层优选地是用于通用的先前制造的部件 多应用程序使用，不一定限于其对特定应用程序的使用。 VSI集成方法通过消除或减少电路设计，布局，工具和制造成本降低了低容量定制电子产品与大容量通用电子产品之间的成本差异。