Abstract:
Methods and apparatus for determining whether a substrate includes an unacceptably high amount of oxide on its surface are described. The substrate is typically a substrate that is to be electroplated. The determination may be made directly in an electroplating apparatus, during an initial portion of an electroplating process. The determination may involve immersing the substrate in electrolyte with a particular applied voltage or applied current provided during or soon after immersion, and recording a current response or voltage response over this same timeframe. The applied current or applied voltage may be zero or non-zero. By comparing the current response or voltage response to a threshold current, threshold voltage, or threshold time, it can be determined whether the substrate included an unacceptably high amount of oxide on its surface. The threshold current, threshold voltage, and/or threshold time may be selected based on a calibration procedure.
Abstract:
본 발명은 고전자이동도 트랜지스터 및 그 제조방법에 관한 것으로, 기판의 상부에 순차적층되는 채널층, 장벽층 및 보호층과, 보호층의 개구 부분을 통해 노출되는 보호층의 하부층에 접촉되는 소스 전극, 드레인 전극 및 게이트 전극을 포함하는 고전자이동도 트랜지스터에 있어서, 상기 소스 전극과 상기 드레인 전극의 상부를 노출시키도록 상기 보호층 및 게이트 전극의 상부 전면에 위치하는 패시베이션층과, 상기 소스 전극과 상기 드레인 전극 각각의 상부에 위치하는 소스 전극 패드와 드레인 전극 패드와, 상기 소스 전극 패드에 연결되어 상기 게이트 전극 상의 상기 패시베이션층으로 연장된 전기도금 필드 플레이트를 포함한다.
Abstract:
본 발명은 기판 위에 비진공 상태의 전기증착을 이용하여 반투명막층이 형성되는 S1 단계; 및 반투명막층 위에 비진공 상태의 전기증착을 이용하여 활성층이 형성되는 S2 단계를 포함하며, 반투명막층에서 특정방향의 우선배향성이 정해지고, 활성층은 반투명막층에서 정해진 특정방향으로 성장하는 것을 특징으로 하는 가시광영역의 흡수성 특성을 갖는 산화물반도체 제조방법에 관한 것이다. 저온 전기증착 공정으로 성장된 p형 산화물 반도체의 단점인 높은 비저항 문제를, 금속 계면활성제를 통해 전기화학적 성장 거동을 제어하여 해결하는 효과가 있다.
Abstract:
A system for controlling the operation of apparatus for electroplating semiconductor substrates includes operating in a high mode of operation in which an off-the-shelf power supply provides current or voltage that is directly used to produce the channel control signal and in a low mode of operation in which the off-the-shelf power supply biases a circuit that provides a current or voltage to produce the channel control signal.
Abstract:
The invention relates to an aqueous plating bath composition and a method for depositing a palladium layer by electroless plating onto a substrate. The aqueous plating bath composition according to the invention comprises a source for palladium ions, a reducing agent for palladium ions and an unsaturated compound. The aqueous plating bath composition according to the invention has an improved stability against undesired decomposition due to the unsaturated compounds while keeping the deposition rate for palladium at the desired satisfying value. The aqueous plating bath composition has also a prolonged life time. The unsaturated compounds of the invention allow for adjusting the deposition rate to a satisfying range over the bath life time and for electrolessly depositing palladium layers at lower temperatures.
Abstract:
An electroplating system includes a processor has a vessel having a first or upper compartment and a second or lower compartment containing catholyte and anolyte, respectively, with an processor anionic membrane between them. An inert anode is located in the second compartment. A replenisher is connected to the vessel via catholyte return and supply lines and anolyte return and supply lines, to circulate catholyte and anolyte through compartments in the replenisher separated by a replenisher anionic membrane. The replenisher adds metal ions into the catholyte by moving ions from a bulk metal source, and moves anions from the anolyte through the anionic membrane and into the catholyte. Concentrations or metal ions and anions in the catholyte and the anolyte remain balanced.
Abstract:
In electroplating apparatus, a paddle or agitator agitates electrolyte in a vessel to provide high velocity fluid flow at the surface of a wafer. The agitator is designed and/or moved to also selectively shield part of the wafer, for example the edge of the wafer, from the electric field in the vessel. Selectively shielding may be achieved by temporally shifting the average position of the agitator towards one side of the wafer, by omitting or shortening slots in the agitator, and/or by synchronizing movement of the agitator with rotation of the wafer.