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    SYSTEMS, METHODS, AND APPARATUS FOR SEMICONDUCTOR MEMORY WITH POROUS ACTIVE LAYER
    31.
    发明申请
    SYSTEMS, METHODS, AND APPARATUS FOR SEMICONDUCTOR MEMORY WITH POROUS ACTIVE LAYER 审中-公开

    公开(公告)号：WO2018125238A1

    公开(公告)日：2018-07-05

    申请号：PCT/US2016/069619

    申请日：2016-12-30

    Applicant: INTEL CORPORATION

    Inventor： BIELEFELD, Jeffery D. ,  KING, Sean W. ,  KARPOV, Elijah V. ,  CLARKE, James S.

    IPC: H01L45/00

    CPC classification number: H01L45/085 ,  H01L45/00 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/146 ,  H01L45/149 ,  H01L45/16

    Abstract: In various embodiments, low-density dielectrics (for example, interlayer dielectrics, ILDs) can be used as the active layer in conduction bridging random access memory (CBRAM) devices. Further, such low-density dielectrics may permit a predetermined level of metal migration in the active layer of the device. In one embodiment, the density and/or porosity of the active layer can be adjusted to affect the performance of the device. In various embodiments, the disclosure describes the use of such porous and/or low-density dielectric layers (for example, silicon oxycarbide, SiOC, silicon carbide, SiC, silicon carbon nitride, SiCN, silicon oxycarbonitride, SiOCN, silicon nitride, SiNx, and the like) as the solid electrolyte comprising the active layer in CBRAM devices. In an embodiment, the use of these porous and/or low-density backend dielectric materials as the active layer can permit filament formation voltages less than approximately 2 V.

    SPACER-BASED PATTERNING FOR TIGHT-PITCH AND LOW-VARIABILITY RANDOM ACCESS MEMORY (RAM) BIT CELLS AND THE RESULTING STRUCTURES
    32.
    发明申请
    SPACER-BASED PATTERNING FOR TIGHT-PITCH AND LOW-VARIABILITY RANDOM ACCESS MEMORY (RAM) BIT CELLS AND THE RESULTING STRUCTURES 审中-公开
    用于间距和低变量随机访问存储器（RAM）位单元的细胞间距图形和结果结构

    公开(公告)号：WO2018063322A1

    公开(公告)日：2018-04-05

    申请号：PCT/US2016/054760

    申请日：2016-09-30

    Applicant: INTEL CORPORATION

    Inventor： LIN, Kevin L. ,  ATANASOV, Sarah E. ,  O'BRIEN, Kevin P. ,  BRISTOL, Robert L.

    IPC: H01L45/00

    CPC classification number: H01L45/146 ,  H01L27/2436 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/00 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/124 ,  H01L45/1266 ,  H01L45/141 ,  H01L45/147 ,  H01L45/1675

    Abstract: Spacer-based patterning for tight-pitch and low-variability random access memory (RAM) bit cells, and the resulting structures, are described. In an example, a semiconductor structure includes a substrate having a top layer. An array of non-volatile random access memory (RAM) bit cells is disposed on the top layer of the substrate. The array of non-volatile RAM bit cells includes columns of non-volatile RAM bit cells along a first direction and rows of non-volatile RAM bit cells along a second direction orthogonal to the first direction. A plurality of recesses is in the top layer of the substrate, along the first direction between columns of the array of non-volatile RAM bit cells.

    Abstract translation: 描述了用于窄间距和低变异性随机存取存储器（RAM）位单元的基于间隔的图案化以及所产生的结构。 在一个示例中，半导体结构包括具有顶层的衬底。 非易失性随机存取存储器（RAM）位单元的阵列设置在衬底的顶层上。 非易失性RAM位单元阵列包括沿着第一方向的非易失性RAM位单元的列和沿着与第一方向正交的第二方向的非易失性RAM位单元的行。 沿着非易失性RAM位单元阵列的列之间的第一方向，衬底的顶层中有多个凹槽。

    RESISTIVE RANDOM ACCESS MEMORY DEVICES
    33.
    发明申请
    RESISTIVE RANDOM ACCESS MEMORY DEVICES 审中-公开
    随机访问存储器设备

    公开(公告)号：WO2018044256A1

    公开(公告)日：2018-03-08

    申请号：PCT/US2016/049196

    申请日：2016-08-29

    Applicant: INTEL CORPORATION

    Inventor： MAJHI, Prashant ,  PILLARISETTY, Ravi ,  KARPOV, Elijah V. ,  MUKHERJEE, Niloy ,  CLARKE, James S.

    IPC: H01L45/00

    CPC classification number: H01L27/2436 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/145 ,  H01L45/146 ,  H01L45/16

    Abstract: Disclosed herein are resistive random access memory (RRAM) devices, and related memory cells and electronic devices. In some embodiments, an RRAM device may include a bottom electrode, an oxygen exchange layer (OEL), and an oxide layer. The bottom electrode may be disposed between the OEL and a substrate, and the OEL may be disposed between the oxide layer and the bottom electrode.

    Abstract translation: 这里公开的是电阻式随机存取存储器（RRAM）器件，以及相关的存储器单元和电子器件。 在一些实施例中，RRAM器件可以包括底部电极，氧气交换层（OEL）和氧化物层。 底部电极可以设置在OEL和衬底之间，并且OEL可以设置在氧化物层和底部电极之间。

    NONVOLATILE BIPOLAR JUNCTION MEMORY CELL
    34.
    发明申请
    NONVOLATILE BIPOLAR JUNCTION MEMORY CELL 审中-公开
    非易失性双极结型存储单元

    公开(公告)号：WO2017189082A1

    公开(公告)日：2017-11-02

    申请号：PCT/US2017/019165

    申请日：2017-02-23

    Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.

    Inventor： BEDAU, Daniel

    IPC: H01L27/24

    CPC classification number: H01L45/1206 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/1226 ,  H01L45/1266 ,  H01L45/146

    Abstract: The present disclosure generally relates to an apparatus for a three terminal nonvolatile memory cell. Specifically, a three terminal nonvolatile bipolar junction transistor. The bipolar junction memory device includes a collector layer, a base layer disposed on the collector layer, an emitter layer disposed on the base layer, and a conductive anodic filament extending from the collector layer to the base layer. As current is applied to the transistor and a voltage is applied between P-N junction of the collector layer and the base layer, a conductive anodic filament (CAF) forms. The CAF is non-volatile and short circuits the reverse-biased P-N junction barrier thus keeping the device in a low-resistive state. Removing the CAF switches the device back to a high resistive state. Thus, a new type of semiconductor device advantageously combines computation and memory to form a flux-linkage modulated memory cell.

    Abstract translation: 本公开一般涉及用于三端子非易失性存储器单元的设备。 具体而言，三端非易失性双极结型晶体管。 双极结存储器件包括集电极层，设置在集电极层上的基极层，设置在基极层上的发射极层以及从集电极层延伸到基极层的导电阳极丝。 当电流施加到晶体管并且在集电极层的P-N结和基极层之间施加电压时，形成导电阳极丝（CAF）。 CAF是非易失性的，将反向偏置的P-N结势垒短路，从而保持器件处于低电阻状态。 移除CAF可将设备切换回高电阻状态。 因此，新型半导体器件有利地将计算和存储器组合在一起以形成磁通调制存储器单元。

    NON-VOLATILE RESISTANCE MEMORY DEVICES INCLUDING A VOLATILE SELECTOR
    36.
    发明申请
    NON-VOLATILE RESISTANCE MEMORY DEVICES INCLUDING A VOLATILE SELECTOR 审中-公开
    非易失性存储器件，包括一个易失性选择器

    公开(公告)号：WO2016182562A1

    公开(公告)日：2016-11-17

    申请号：PCT/US2015/030370

    申请日：2015-05-12

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： ZHANG, Minxian Max ,  YANG, Jianhua ,  WILLIAMS, R. Stanley ,  SAMUELS, Katy ,  LI, Zhiyong

    IPC: G11C13/00

    CPC classification number: G11C13/003 ,  G11C13/0007 ,  G11C13/0011 ,  G11C2213/32 ,  G11C2213/51 ,  G11C2213/76 ,  H01L27/2409 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/145 ,  H01L45/146 ,  H01L45/16

    Abstract: A nonvolatile memory cell includes a volatile selector electrically coupled in series with a nonvolatile memory device. The nonvolatile memory device includes a switching oxide or switching nitride sandwiched between a first bottom electrode and a first top electrode. The volatile selector includes a selector oxide matrix sandwiched between a second bottom electrode and a second top electrode. The selector oxide matrix may be composed of either copper oxide, silicon dioxide, or a mixture of copper oxide and silicon dioxide. One or both of the second bottom electrode and the second top electrode may be composed of silver. A memory array including a plurality of the nonvolatile memory cells is also disclosed, as is a method for manufacturing the array.

    Abstract translation: 非易失性存储单元包括与非易失性存储器件串联电耦合的易失性选择器。 非易失性存储器件包括夹在第一底部电极和第一顶部电极之间的开关氧化物或切换氮化物。 易失性选择器包括夹在第二底部电极和第二顶部电极之间的选择器氧化物矩阵。 选择氧化物基质可以由氧化铜，二氧化硅或氧化铜和二氧化硅的混合物组成。 第二底部电极和第二顶部电极中的一个或两个可以由银构成。 还公开了包括多个非易失性存储器单元的存储器阵列，以及用于制造阵列的方法。

    STACKED BI-LAYER AS THE LOW POWER SWITCHABLE RRAM
    40.
    发明申请
    STACKED BI-LAYER AS THE LOW POWER SWITCHABLE RRAM 审中-公开
    堆叠双层作为低功率可切换RRAM

    公开(公告)号：WO2015100093A1

    公开(公告)日：2015-07-02

    申请号：PCT/US2014/070767

    申请日：2014-12-17

    Applicant: INTERMOLECULAR, INC.

    Inventor： WANG, Yun ,  NARDI, Federico ,  WELING, Milind

    IPC: H01L29/02

    CPC classification number: H01L45/1266 ,  H01L27/2409 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/1253 ,  H01L45/145 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1625 ,  H01L45/1633

    Abstract: Provided are resistive random access memory (ReRAM) cells and methods of fabricating thereof. The resistive switching nonvolatile memory cells may include a first layer disposed. The first layer may be operable as a bottom electrode. The resistive switching nonvolatile memory cells may also include a second layer disposed over the first layer. The second layer may be operable as a resistive switching layer that is configured to switch between a first resistive state and a second resistive state. The resistive switching nonvolatile memory cells may include a third layer disposed over the second layer. The third layer may be operable as a resistive layer that is configured to determine, at least in part, an electrical resistivity of the resistive switching nonvolatile memory element. The third layer may include a semi-metallic material. The resistive switching nonvolatile memory cells may include a fourth layer that may be operable as a top electrode.

    Abstract translation: 提供了电阻随机存取存储器（ReRAM）单元及其制造方法。 电阻式开关非易失性存储单元可以包括设置的第一层。 第一层可以用作底部电极。 电阻式开关非易失性存储单元还可以包括设置在第一层上的第二层。 第二层可以用作电阻性开关层，其被配置为在第一电阻状态和第二电阻状态之间切换。 电阻式开关非易失性存储单元可以包括设置在第二层上的第三层。 第三层可以用作电阻层，其被配置为至少部分地确定电阻式开关非易失性存储元件的电阻率。 第三层可以包括半金属材料。 电阻式开关非易失性存储单元可以包括可用作顶部电极的第四层。

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