中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

175 records (took 0.016 seconds)

    HYBRID ORIENTATION FIN FIELD EFFECT TRANSISTOR AND PLANAR FIELD EFFECT TRANSISTOR
    71.
    发明申请
    HYBRID ORIENTATION FIN FIELD EFFECT TRANSISTOR AND PLANAR FIELD EFFECT TRANSISTOR 审中-公开
    混合磁场效应晶体管和平面场效应晶体管

    公开(公告)号：WO2014058552A1

    公开(公告)日：2014-04-17

    申请号：PCT/US2013/058671

    申请日：2013-09-09

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： CHENG, Kangguo ,  HARAN, Balasubramanian, S. ,  PONOTH, Shom ,  STANDAERT, Theodorus, E. ,  YAMASHITA, Tenko

    IPC: H01L29/78 ,  H01L21/336

    CPC classification number: H01L29/7848 ,  H01L21/76283 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823864 ,  H01L21/823878 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/045 ,  H01L29/0653 ,  H01L29/0847

    Abstract: A substrate including a handle substrate (10), a lower insulator layer (20), a buried semiconductor layer (30L), an upper insulator layer (40L), and a top semiconductor layer (50L) is provided. Semiconductor fins (32) can be formed by patterning a portion of the buried semiconductor layer (30L) after removal of the upper insulator layer (40L) and the top semiconductor layer (50L) in a fin region, while a planar device region is protected by an etch mask. A disposable fill material portion (59) is formed in the fin region, and a shallow trench isolation structure (41) can be formed in the planar device region. The disposable fill material portion (59) is removed, and gate stacks for a planar field effect transistor and a fin field effect transistor can be simultaneously formed. Alternately, disposable gate structures and a planarization dielectric layer can be formed, and replacement gate stacks can be subsequently formed.

    Abstract translation: 提供了包括手柄基板（10），下绝缘体层（20），埋入半导体层（30L），上绝缘体层（40L）和顶部半导体层（50L）的基板。 半导体翅片（32）可以通过在散热片区域中去除上部绝缘体层（40L）和顶部半导体层（50L）之后对掩埋半导体层（30L）的一部分进行构图而形成，而平面器件区域被保护 通过蚀刻掩模。 在翅片区域中形成一次性填充材料部分（59），并且可以在平面装置区域中形成浅沟槽隔离结构（41）。 一次性填充材料部分（59）被去除，并且可以同时形成用于平面场效应晶体管和鳍式场效应晶体管的栅极叠层。 或者，可以形成一次性栅极结构和平坦化介电层，并且随后可以形成替换栅极叠层。

    STRAINED GATE-ALL-AROUND SEMICONDUCTOR DEVICES FORMED ON GLOBALLY OR LOCALLY ISOLATED SUBSTRATES
    73.
    发明申请
    STRAINED GATE-ALL-AROUND SEMICONDUCTOR DEVICES FORMED ON GLOBALLY OR LOCALLY ISOLATED SUBSTRATES 审中-公开
    在全球或当地分离的基底上形成的应变栅格全面的半导体器件

    公开(公告)号：WO2014051728A2

    公开(公告)日：2014-04-03

    申请号：PCT/US2013/045217

    申请日：2013-06-11

    Applicant: INTEL CORPORATION

    Inventor： CAPPELLANI, Annalisa ,  PETHE, Abhijit Jayant ,  GHANI, Tahir ,  GOMEZ, Harry ,  KIM, Seiyon

    CPC classification number: H01L29/42392 ,  B82Y10/00 ,  H01L21/30604 ,  H01L21/845 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/401 ,  H01L29/41725 ,  H01L29/42356 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/78696

    Abstract: Strained gate-all-around semiconductor devices formed on globally or locally isolated substrates are described. For example, a semiconductor device includes a semiconductor substrate. An insulating structure is disposed above the semiconductor substrate. A three-dimensional channel region is disposed above the insulating structure. Source and drain regions are disposed on either side of the three-dimensional channel region and on an epitaxial seed layer. The epitaxial seed layer is composed of a semiconductor material different from the three-dimensional channel region and disposed on the insulating structure. A gate electrode stack surrounds the three-dimensional channel region with a portion disposed on the insulating structure and laterally adjacent to the epitaxial seed layer.

    Abstract translation: 描述了形成在全局或局部隔离的基板上的应变门全面半导体器件。 例如，半导体器件包括半导体衬底。 绝缘结构设置在半导体衬底之上。 三维沟道区设置在绝缘结构的上方。 源极和漏极区域设置在三维沟道区域的两侧和外延晶种层上。 外延种子层由不同于三维沟道区的半导体材料构成，并且设置在绝缘结构上。 栅极电极堆叠围绕三维沟道区域，其中设置在绝缘结构上的部分并且横向邻近外延籽晶层。

    PASSIVE DEVICES FOR FINFET INTEGRATED CIRCUIT TECHNOLOGIES
    74.
    发明申请
    PASSIVE DEVICES FOR FINFET INTEGRATED CIRCUIT TECHNOLOGIES 审中-公开
    FINFET集成电路技术的被动设备

    公开(公告)号：WO2013148079A1

    公开(公告)日：2013-10-03

    申请号：PCT/US2013/028965

    申请日：2013-03-05

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： CLARK, William, F. ,  GAUTHIER, Robert, J. ,  LI, Junjun

    IPC: H01L27/108

    CPC classification number: H01L21/845 ,  H01L27/0262 ,  H01L27/1211

    Abstract: Device structures, design structures, and fabrication methods for passive devices that may be used as electrostatic discharge protection devices in fin-type field-effect transistor integrated circuit technologies. A device structure is formed that includes a well (12) of a first conductivity type in a device region (22) and a doped region (52) of a second conductivity in the well. The device region is comprised of a portion of a device layer (14) of a semiconductor-on-insulator substrate (10). The doped region and a first portion of the well (57) define a junction (65). A second portion of the well (61) is positioned between the doped region (62) and an exterior sidewall (23) of the device region. Another portion of the device layer may be patterned to form fins for fin-type field-effect transistors.

    Abstract translation: 无源器件的器件结构，设计结构和制造方法，可用作鳍式场效应晶体管集成电路技术中的静电放电保护器件。 形成器件结构，其在器件区域（22）中包括第一导电类型的阱（12）和阱中的第二导电性的掺杂区域（52）。 器件区域由绝缘体上半导体衬底（10）的器件层（14）的一部分组成。 掺杂区域和阱（57）的第一部分限定结（65）。 阱（61）的第二部分位于装置区域的掺杂区域（62）和外侧壁（23）之间。 可以对器件层的另一部分进行图案化以形成翅片型场效应晶体管的鳍片。

    SEMICONDUCTOR DEVICES HAVING FIN STRUCTURES AND FABRICATION METHODS THEREOF
    76.
    发明申请
    SEMICONDUCTOR DEVICES HAVING FIN STRUCTURES AND FABRICATION METHODS THEREOF 审中-公开
    具有鳍结构的半导体器件及其制造方法

    公开(公告)号：WO2013022753A2

    公开(公告)日：2013-02-14

    申请号：PCT/US2012049531

    申请日：2012-08-03

    Applicant: HOFFMANN THOMAS ,  THOMPSON SCOTT E ,  SUVOLTA INC

    Inventor： HOFFMANN THOMAS ,  THOMPSON SCOTT E

    IPC: H01L29/78 ,  H01L21/336

    CPC classification number: H01L21/823828 ,  H01L21/823431 ,  H01L21/845 ,  H01L29/1083 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7853

    Abstract: A method of fabricating semiconductor devices includes providing a semiconducting substrate. The method also includes defining a heavily doped region at a surface of the semiconducting substrate in at least one area of the semiconducting substrate, where the heavily doped region includes a heavily doped layer having a doping concentration greater than a doping concentration of the semiconducting substrate. The method also includes forming an additional layer of semiconductor material on the semiconducting substrate, the additional layer comprising a substantially undoped layer. The method further includes applying a first removal process to the semiconducting substrate to define an unetched portion and an etched portion, where the unetched portion defines a fin structure, and the etched portion extends through the additional layer, and then isolating the fin structure from other structures.

    Abstract translation: 制造半导体器件的方法包括提供半导体衬底。 该方法还包括在半导体衬底的至少一个区域中的半导体衬底的表面处限定重掺杂区域，其中重掺杂区域包括掺杂浓度大于半导体衬底的掺杂浓度的重掺杂层。 该方法还包括在半导体衬底上形成附加层的半导体材料，附加层包括基本上未掺杂的层。 该方法进一步包括对半导体衬底应用第一去除工艺以限定未刻蚀部分和刻蚀部分，其中未刻蚀部分限定鳍结构，并且刻蚀部分延伸穿过额外层，然后将鳍结构与其他层 结构。

    THRESHOLD ADJUSTMENT OF TRANSISTORS BY CONTROLLED S/D UNDERLAP
    77.
    发明申请
    THRESHOLD ADJUSTMENT OF TRANSISTORS BY CONTROLLED S/D UNDERLAP 审中-公开
    通过控制的S / D底线调整晶体管的阈值

    公开(公告)号：WO2013016089A1

    公开(公告)日：2013-01-31

    申请号：PCT/US2012/047120

    申请日：2012-07-18

    Applicant: SYNOPSYS, INC. ,  MOROZ, Victor ,  SPROCH, James, D.

    Inventor： MOROZ, Victor ,  SPROCH, James, D.

    IPC: H01L29/78 ,  H01L21/336

    CPC classification number: H01L27/1203 ,  H01L21/84 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/78618

    Abstract: Roughly described, an integrated circuit device has formed on a substrate a plurality of transistors including a first subset of at least one transistor and a second subset of at least one transistor, wherein all of the transistors in the first subset have one underlap distance and all of the transistors in the second subset have a different underlap distance. The transistors in the first and second subsets preferably have different threshold voltages, and preferably realize different points on the high performance/low power tradeoff.

    Abstract translation: 粗略地描述，集成电路器件已经在衬底上形成多个晶体管，其包括至少一个晶体管的第一子集和至少一个晶体管的第二子集，其中第一子集中的所有晶体管具有一个下层距离，并且全部 的第二子集中的晶体管具有不同的底层距离。 第一和第二子集中的晶体管优选地具有不同的阈值电压，并且优选地在高性能/低功率权衡上实现不同的点。

    INTEGRATED FIN-BASED FIELD EFFECT TRANSISTOR (FINFET) AND METHOD OF FABRICATION OF SAME
    80.
    发明申请
    INTEGRATED FIN-BASED FIELD EFFECT TRANSISTOR (FINFET) AND METHOD OF FABRICATION OF SAME 审中-公开
    集成的FIN基场效应晶体管（FINFET）及其制造方法

    公开(公告)号：WO2012018789A1

    公开(公告)日：2012-02-09

    申请号：PCT/US2011/046230

    申请日：2011-08-02

    Applicant: ADVANCED MICRO DEVICES, INC. ,  SCHULTZ, Richard, T.

    Inventor： SCHULTZ, Richard, T.

    IPC: H01L29/78 ,  H01L21/336 ,  H01L21/84 ,  H01L27/12

    CPC classification number: H01L27/1211 ,  H01L21/845 ,  H01L29/66795 ,  H01L29/785

    Abstract: An integrated fin-based field effect transistor (FinFET) and method of fabricating such devices on a bulk wafer with EPI-defined fin heights over shallow trench isolation (STI) regions. The FinFET channels overlie the STI regions within the semiconductor bulk, while the fins extend beyond the STI regions into the source and drain regions which are implanted within the semiconductor bulk. With bulk source and drain regions, reduced external FinFET resistance is provided, and with the fins extending into the bulk source and drain regions, improved thermal properties is provided over conventional silicon on insulator (SOI) devices.

    Abstract translation: 集成的鳍状场效应晶体管（FinFET）以及在浅沟槽隔离（STI）区域上具有EPI限定的鳍高度的体晶片上制造这种器件的方法。 FinFET通道覆盖半导体本体内的STI区域，而散热片延伸超出STI区域进入注入半导体本体的源极和漏极区域。 对于体源极和漏极区域，提供了减小的外部FinFET电阻，并且翅片延伸到体源极和漏极区域中，在传统的绝缘体上硅（SOI）器件上提​​供了改进的热性能。

Patent Agency Ranking