公开(公告)号：WO2013101123A1

公开(公告)日：2013-07-04

申请号：PCT/US2011/067970

申请日：2011-12-29

Applicant: INTEL CORPORATION ,  VERA, Xavier ,  MONCHIERO, Matteo ,  CASADO, Javier, Carretero ,  HERRERO, Enric ,  RAMIREZ, Tanausu

Inventor： VERA, Xavier ,  MONCHIERO, Matteo ,  CASADO, Javier, Carretero ,  HERRERO, Enric ,  RAMIREZ, Tanausu

IPC: G06F11/08 ,  G06F12/16 ,  G06F15/80

CPC classification number: G06F12/0822 ,  G06F11/00 ,  G06F11/08 ,  G06F11/1666 ,  G06F11/20 ,  G06F12/0806 ,  G06F12/0815 ,  G06F12/0817 ,  G06F12/12 ,  G06F2212/1024 ,  G06F2212/1028 ,  G06F2212/1044 ,  Y02D10/13

Abstract: Some implementations disclosed herein provide techniques and arrangements for recovery of data stored in memory shared by a number of processors through information stored in a cache directory. A core of a processor may initiate access (e.g., read or write) to particular data located in a first cache that is accessible to the core. In response to detecting an error associated with accessing the particular data, a location in the processor that includes the particular data may be identified and the particular data may be copied from the location to the first cache.

Abstract translation: 本文公开的一些实现方式提供了通过存储在高速缓存目录中的信息来恢复存储在由多个处理器共享的存储器中的数据的技术和装置。 处理器的核心可以启动对位于核心可访问的第一高速缓存中的特定数据的访问（例如，读或写）。 响应于检测到与访问特定数据相关联的错误，可以识别包括特定数据的处理器中的位置，并且可以将特定数据从该位置复制到第一高速缓存。

公开(公告)号：WO2013101050A1

公开(公告)日：2013-07-04

申请号：PCT/US2011/067824

申请日：2011-12-29

Applicant: INTEL CORPORATION ,  FANNING, Blaise ,  QAWAMI, Shekoufeh ,  TETRICK, Raymond S. ,  HADY, Frank T.

Inventor： FANNING, Blaise ,  QAWAMI, Shekoufeh ,  TETRICK, Raymond S. ,  HADY, Frank T.

IPC: G06F12/00 ,  G11C13/02 ,  G11C16/00

CPC classification number: G06F3/0644 ,  G06F3/0604 ,  G06F3/0631 ,  G06F3/0679 ,  G06F3/0688 ,  G06F12/023 ,  G06F12/0238 ,  G06F12/0246 ,  G06F12/08 ,  G06F12/10 ,  G06F12/1009 ,  G06F2212/2024 ,  G06F2212/205 ,  G06F2212/7201 ,  G06F2212/7204 ,  G11C7/1006 ,  G11C11/56 ,  G11C16/00 ,  Y02D10/13

Abstract: Embodiments of a method, device, and system for implementing multi-level memory with direct access are disclosed. In one embodiment, the method includes designating an amount of a non-volatile random access memory (NVRAM) in a computer system to be utilized as a memory alternative for a dynamic random access memory (DRAM). The method continues by designating a second amount of the NVRAM to be utilized as a storage alternative for a mass storage device. Then the method re-designates at least a first portion of the first amount of NVRAM from the memory alternative designation to the storage alternative designation during operation of the computer system. Finally, the method re-designates at least a first portion of the second amount of NVRAM from the storage alternative designation to the memory alternative designation during operation of the computer system.

Abstract translation: 公开了用于实现具有直接访问的多级存储器的方法，设备和系统的实施例。 在一个实施例中，该方法包括指定要用作动态随机存取存储器（DRAM）的存储器备选方案的计算机系统中的非易失性随机存取存储器（NVRAM）的量。 该方法通过指定要用作大容量存储设备的存储备用的第二数量的NVRAM来继续。 然后，该方法在计算机系统的操作期间将存储器备选指定中的第一数量的NVRAM的至少第一部分重新指定为存储备选指定。 最后，该方法在计算机系统的操作期间将第二数量的NVRAM的至少第一部分从存储替代指定重新指定到存储器备选指定。

公开(公告)号：WO2013100913A1

公开(公告)日：2013-07-04

申请号：PCT/US2011/067422

申请日：2011-12-27

Applicant: INTEL CORPORATION ,  AHUJA, Sandeep ,  SAUCIUC, Ioan ,  SMITH, Susan F.

Inventor： AHUJA, Sandeep ,  SAUCIUC, Ioan ,  SMITH, Susan F.

IPC: H01L21/02

CPC classification number: H01L23/473 ,  G06F1/206 ,  H01L23/34 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Thermal management systems for semiconductor devices are provided. Embodiments of the invention provide two or more liquid cooling subsystems that are each capable of providing active cooling to one or more semiconductor devices, such as packaged processors. In operation, a first liquid cooling subsystem can provide active cooling to the semiconductor device(s) while the second cooling subsystem is circulating a heat transfer fluid within its own subsystem. The second liquid cooling subsystem can be then switched into operation and provides active cooling to the semiconductor device(s) while the first cooling subsystem is circulating heat transfer fluid within its own subsystem. In alternate embodiments, the heat transfer fluid remains in the subsystem, but does not circulate within the subsystem when the subsystem is not providing cooling to the semiconductor device(s). The subsystems comprise heat dissipation units. The switching between cooling systems allows the semiconductor device(s) to be maintained at a lower operating temperature than if switching between cooling subsystems were not employed.

Abstract translation: 提供半导体器件的热管理系统。 本发明的实施例提供两个或更多个液体冷却子系统，每个液体冷却子系统能够向一个或多个半导体器件（例如封装的处理器）提供主动冷却。 在操作中，第一液体冷却子系统可以向半导体器件提供主动冷却，而第二冷却子系统在其自身子系统内循环传热流体。 然后可以将第二液体冷却子系统切换到操作中，并且在第一冷却子系统在其自己的子系统内循环传热流体时，向半导体装置提供主动冷却。 在替代实施例中，传热流体保留在子系统中，但是当子系统不向半导体器件提供冷却时，该子系统不会在子系统内循环。 子系统包括散热单元。 冷却系统之间的切换允许半导体器件保持在比不使用冷却子系统之间切换的较低的工作温度。

公开(公告)号：WO2013095643A1

公开(公告)日：2013-06-27

申请号：PCT/US2011/067220

申请日：2011-12-23

Applicant: INTEL CORPORATION ,  THEN, Han Wui ,  RADOSAVLJEVIC, Marko ,  SHAH, Uday ,  MUKHERJEE, Niloy ,  PILLARISETTY, Ravi ,  CHU-KUNG, Benjamin ,  KAVALIEROS, Jack ,  CHAU, Robert

Inventor： THEN, Han Wui ,  RADOSAVLJEVIC, Marko ,  SHAH, Uday ,  MUKHERJEE, Niloy ,  PILLARISETTY, Ravi ,  CHU-KUNG, Benjamin ,  KAVALIEROS, Jack ,  CHAU, Robert

IPC: H01L29/772 ,  H01L21/335

CPC classification number: H01L29/7787 ,  H01L21/02241 ,  H01L21/02252 ,  H01L21/02255 ,  H01L21/02258 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/268 ,  H01L21/30604 ,  H01L21/30612 ,  H01L21/31111 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/365 ,  H01L29/401 ,  H01L29/4236 ,  H01L29/512 ,  H01L29/518 ,  H01L29/66462

Abstract: III-N transistors with recessed gates. An epitaxial stack includes a doped III-N source/drain layer and a III-N etch stop layer disposed between a the source/drain layer and a III-N channel layer. An etch process, e.g., utilizing photochemical oxidation, selectively etches the source/drain layer over the etch stop layer. A gate electrode is disposed over the etch stop layer to form a recessed-gate III-N HEMT. At least a portion of the etch stop layer may be oxidized with a gate electrode over the oxidized etch stop layer for a recessed gate III-N MOS-HEMT including a III-N oxide. A high-k dielectric may be formed over the oxidized etch stop layer with a gate electrode over the high-k dielectric to form a recessed gate III-N MOS-HEMT having a composite gate dielectric stack.

Abstract translation: 具有凹入栅极的III-N晶体管。 外延堆叠包括掺杂的III-N源极/漏极层和设置在源/漏层和II​​I-N沟道层之间的III-N蚀刻停止层。 蚀刻工艺，例如利用光化学氧化，选择性地蚀刻蚀刻停止层上的源极/漏极层。 栅电极设置在蚀刻停止层上方以形成凹入栅III-N HEMT。 蚀刻停止层的至少一部分可以用氧化蚀刻停止层上的栅电极氧化，用于包括III-N氧化​​物的凹陷栅III-N MOS-HEMT。 可以在氧化的蚀刻停止层上形成高k电介质，并在高k电介质上形成栅电极，以形成具有复合栅电介质叠层的凹陷栅III-N MOS-HEMT。

公开(公告)号：WO2013095467A1

公开(公告)日：2013-06-27

申请号：PCT/US2011/066652

申请日：2011-12-21

Applicant: INTEL CORPORATION ,  BASEL, Adi ,  HILDESHEIM, Gur ,  RAIKIN, Shlomo ,  CHAPPELL, Robert ,  KIM, Ho-Seop ,  BHATIA, Rohit

Inventor： BASEL, Adi ,  HILDESHEIM, Gur ,  RAIKIN, Shlomo ,  CHAPPELL, Robert ,  KIM, Ho-Seop ,  BHATIA, Rohit

IPC: G06F1/00

CPC classification number: G06F12/122 ,  G06F3/0604 ,  G06F12/00 ,  G06F12/0842 ,  G06F12/0864 ,  G06F12/124 ,  G06F12/125

Abstract: In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for implementing a balanced P-LRU tree for a "multiple of 3" number of ways cache. For example, in one embodiment, such means may include an integrated circuit having a cache and a plurality of ways. In such an embodiment the plurality of ways include a quantity that is a multiple of three and not a power of two, and further in which the plurality of ways are organized into a plurality of pairs. In such an embodiment, means further include a single bit for each of the plurality of pairs, in which each single bit is to operate as an intermediate level decision node representing the associated pair of ways and a root level decision node having exactly two individual bits to point to one of the single bits to operate as the intermediate level decision nodes representing an associated pair of ways. In this exemplary embodiment, the total number of bits is N-1, wherein N is the total number of ways in the plurality of ways. Alternative structures are also presented for full LRU implementation, a "multiple of 5" number of cache ways, and variations of the "multiple of 3" number of cache ways.

Abstract translation: 根据本文公开的实施例，提供了用于实现用于“3”倍的方式高速缓存的平衡P-LRU树的方法，系统，机制，技术和装置。 例如，在一个实施例中，这种装置可以包括具有高速缓存和多个方式的集成电路。 在这样的实施例中，多个方式包括一个数量是三的倍数，而不是二的幂，并且其中多个方式被组织成多对。 在这样的实施例中，装置还包括用于多个对中的每一对的单个位，其中每个单个位将用作表示相关联的方式的中间级决策节点和具有正好两个单独位的根级判定节点 指向要作为表示相关联的方式的中间级决策节点操作的单个位之一。 在该示例性实施例中，总数是N-1，其中N是多个方式的总路数。 还提供了替代结构，用于完整的LRU实现，“多路复用5”缓存方式，以及“3”倍数缓存方式的变化。

公开(公告)号：WO2013095438A1

公开(公告)日：2013-06-27

申请号：PCT/US2011/066495

申请日：2011-12-21

Applicant: INTEL CORPORATION ,  LINDERT, Nick ,  SINGH, Kanwal Jit ,  LEE, Byung-Chan

Inventor： LINDERT, Nick ,  SINGH, Kanwal Jit ,  LEE, Byung-Chan

IPC: H01L21/28 ,  H01L21/31

CPC classification number: H01L27/0611 ,  H01L21/76841 ,  H01L21/76849 ,  H01L21/76883 ,  H01L23/5223 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Fully encapsulated conductive lines are generally described. For example, a first dielectric layer is formed on a substrate. Copper wiring is disposed below a top surface of the first dielectric layer. A barrier metal layer is formed over the copper wiring, the barrier metal layer flush with the top surface of the first dielectric layer, and a second dielectric layer is formed on the barrier metal layer and the top surface of the first dielectric layer. Other embodiments are also disclosed and claimed.

Abstract translation: 通常描述完全封装的导电线。 例如，在基板上形成第一电介质层。 铜布线设置在第一介电层的顶表面下方。 在铜布线上形成阻挡金属层，阻挡金属层与第一电介质层的顶表面齐平，并且在阻挡金属层和第一介电层的顶表面上形成第二电介质层。 还公开并要求保护其他实施例。

公开(公告)号：WO2013095346A1

公开(公告)日：2013-06-27

申请号：PCT/US2011/065922

申请日：2011-12-19

Applicant: INTEL CORPORATION ,  THEN, Han Wui ,  CHAU, Robert ,  CHU-KUNG, Benjamin ,  DEWEY, Gilbert ,  KAVALIEROS, Jack ,  METZ, Matthew V. ,  MUKHERJEE, Niloy ,  PILLARISETTY, Ravi ,  RADOSAVLJEVIC, Marko

Inventor： THEN, Han Wui ,  CHAU, Robert ,  CHU-KUNG, Benjamin ,  DEWEY, Gilbert ,  KAVALIEROS, Jack ,  METZ, Matthew V. ,  MUKHERJEE, Niloy ,  PILLARISETTY, Ravi ,  RADOSAVLJEVIC, Marko

IPC: H01L29/778 ,  H01L21/335

CPC classification number: H01L29/7787 ,  G06F1/1633 ,  G06F1/189 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/0254 ,  H01L29/045 ,  H01L29/0657 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/402 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/7786 ,  H01L29/7789 ,  H01L29/785 ,  H03F3/195 ,  H03F3/213 ,  H03F2200/451

Abstract: Transistors for high voltage and high frequency operation. A non-planar, polar crystalline semiconductor body having a top surface disposed between first and second opposite sidewalls includes a channel region with a first crystalline semiconductor layer disposed over the first and second sidewalls. The first crystalline semiconductor layer is to provide a two dimensional electron gas (2DEG) within the channel region. A gate structure is disposed over the first crystalline semiconductor layer along at least the second sidewall to modulate the 2DEG. First and second sidewalls of the non-planar polar crystalline semiconductor body may have differing polarity, with the channel proximate to a first of the sidewalls. The gate structure may be along a second of the sidewalls to gate a back barrier. The polar crystalline semiconductor body may be a group III-nitride formed on a silicon substrate with the (101 ?0) plane on a (110) plane of the silicon.

Abstract translation: 用于高压和高频工作的晶体管。 具有设置在第一和第二相对侧壁之间的顶表面的非平面极性结晶半导体本体包括具有设置在第一和第二侧壁上的第一晶体半导体层的沟道区。 第一晶体半导体层是在沟道区内提供二维电子气（2DEG）。 栅极结构沿至少第二侧壁设置在第一晶体半导体层上方，以调制2DEG。 非平面极性结晶半导体主体的第一和第二侧壁可具有不同的极性，其中通道靠近第一侧壁。 栅极结构可以沿着侧壁中的第二侧面以栅极背栅。 极性结晶半导体体可以是在硅衬底上形成的III族氮化物，在硅的（110）平面上具有（101→0）面。

公开(公告)号：WO2013095345A1

公开(公告)日：2013-06-27

申请号：PCT/US2011/065921

申请日：2011-12-19

Applicant: INTEL CORPORATION ,  THEN, Han Wui ,  CHAU, Robert ,  RAO, Valluri ,  MUKHERJEE, Niloy ,  RADOSAVLJEVIC, Marko ,  PILLARISETTY, Ravi ,  DEWEY, Gilbert ,  KAVALIEROS, Jack

Inventor： THEN, Han Wui ,  CHAU, Robert ,  RAO, Valluri ,  MUKHERJEE, Niloy ,  RADOSAVLJEVIC, Marko ,  PILLARISETTY, Ravi ,  DEWEY, Gilbert ,  KAVALIEROS, Jack

IPC: H01L27/00 ,  H01L21/77

CPC classification number: H01L25/072 ,  H01L21/8252 ,  H01L21/8258 ,  H01L25/50 ,  H01L27/0605 ,  H01L27/088 ,  H01L29/2003 ,  H01L29/4236 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/785 ,  H01L2924/0002 ,  H01L2924/00

Abstract: System on Chip (SoC) solutions integrating an RFIC with a PMIC using a transistor technology based on group III-nitrides (III-N) that is capable of achieving high Ft and also sufficiently high breakdown voltage (BV) to implement high voltage and/or high power circuits. In embodiments, the III-N transistor architecture is amenable to scaling to sustain a trajectory of performance improvements over many successive device generations. In embodiments, the III-N transistor architecture is amenable to monolithic integration with group IV transistor architectures, such as planar and non-planar silicon CMOS transistor technologies. Planar and non-planar HEMT embodiments having one or more of recessed gates, symmetrical source and drain, regrown source/drains are formed with a replacement gate technique permitting enhancement mode operation and good gate passivation.

Abstract translation: 片上系统（SoC）解决方案使用基于能够实现高Ft和足够高的击穿电压（BV）的III类氮化物（III-N）的晶体管技术将RFIC与PMIC集成，以实现高电压和/ 或高功率电路。 在实施例中，III-N晶体管架构适于缩放以维持许多连续器件世代的性能改进的轨迹。 在实施例中，III-N晶体管架构适于与IV类晶体管架构（诸如平面和非平面硅CMOS晶体管技术）的单片集成。 具有凹入栅极，对称源极和漏极，再生长源极/漏极中的一个或多个的平面和非平面HEMT实施例使用允许增强模式操作和良好栅极钝化的替代栅极技术形成。

公开(公告)号：WO2013095335A1

公开(公告)日：2013-06-27

申请号：PCT/US2011/065879

申请日：2011-12-19

Applicant: INTEL CORPORATION ,  YE, Xiaoning

Inventor： YE, Xiaoning

IPC: H01R13/658 ,  H01R13/646 ,  H03K19/0175 ,  H04L25/02

CPC classification number: H01P1/227 ,  H01P3/026 ,  H01R13/6471 ,  H04L25/03878 ,  H05K1/0228 ,  H05K1/0245 ,  H05K2201/09236 ,  H05K2201/10189

Abstract: Some embodiments include a first differential signal pair and a second differential signal pair. The first and second differential signal pairs are arranged relative to each other in a manner to intentionally reduce or cancel crosstalk introduced by a pinout (for example, a section of a pinout, a socket, a connector, etc.) into at least one of the first differential signal pair and the second differential signal pair. Other embodiments are described and claimed.

Abstract translation: 一些实施例包括第一差分信号对和第二差分信号对。 第一和第二差分信号对以有意地减少或消除引脚（例如，引脚分布，插座，连接器等的一部分）引入的串扰的方式相对于彼此布置成至少一个 第一差分信号对和第二差分信号对。 描述和要求保护其他实施例。

公开(公告)号：WO2013086218A1

公开(公告)日：2013-06-13

申请号：PCT/US2012/068284

申请日：2012-12-06

Applicant: ACUITAS MEDICAL LIMITED

Inventor： CHASE, David, R. ,  JAMES, Timothy, W. ,  FARR, Lance, W.

IPC: G01R33/483 ,  G01R33/54 ,  G01N24/08

CPC classification number: G01R33/54 ,  G01N24/081 ,  G01R33/4833

Abstract: A method of assessing a spatial frequency distribution within a sample comprising subjecting the sample to magnetic resonance excitation, receiving an echo signal from the sample while the sample is subjected to a magnetic field gradient, applying an invertible linear transform to the echo signal, identifying a region of interest in the transformed echo signal and deriving a corresponding window function, applying the window function (in the signal or transform domain) to the echo signal to remove echo signal coming from regions of the sample outside of the region of interest, and analyzing the one dimensional spatial frequency content in the windowed echo signal in order to access a one dimensional spatial frequency distribution within the region of interest within the sample without creating an image.

Abstract translation: 一种评估样本内的空间频率分布的方法，包括使样本进行磁共振激励，在样本经受磁场梯度的同时接收来自样本的回波信号，对回波信号应用可逆线性变换， 在变换的回波信号中感兴趣的区域并导出对应的窗口函数，将窗函数（在信号或变换域中）应用于回波信号，以去除来自感兴趣区域外的样本区域的回波信号，并分析 窗口回波信号中的一维空间频率内容，以便在样本内访问感兴趣区域内的一维空间频率分布，而不产生图像。