MOSFET WITH GATE PULL-DOWN
    1.
    发明申请
    MOSFET WITH GATE PULL-DOWN 审中-公开
    带有栅极拉下的MOSFET

    公开(公告)号:WO2011079194A3

    公开(公告)日:2011-10-20

    申请号:PCT/US2010061784

    申请日:2010-12-22

    CPC classification number: H03K17/165 H03K17/687

    Abstract: A pull-down MOSFET (110) is coupled between a drain and gate of a MOSFET main switch transistor (102) in a switching type DC-to-DC power converter. A gate of the pull-down MOSFET (110) is coupled to the drain of the main switch transistor (102) by a capacitor 118 and is connected to a source of the main switch transistor (102) by a resistor (120). The pull-down MOSFET (110) is operated by capacitive coupling to the voltage drop across the main switch transistor (102) and can be used to hold the gate of the main switch transistor (102) at or near its source potential to avoid or reduce unintentional turn-on of the main switch transistor (102) by the Miller effect.

    Abstract translation: 下拉MOSFET(110)耦合在开关型DC-DC功率转换器中的MOSFET主开关晶体管(102)的漏极和栅极之间。 下拉MOSFET(110)的栅极通过电容器118耦合到主开关晶体管(102)的漏极,并且通过电阻器(120)连接到主开关晶体管(102)的源极。 下拉MOSFET(110)通过对主开关晶体管(102)两端的电压降进行电容耦合来操作,并且可以用来将主开关晶体管(102)的栅极保持在其源极电位或其附近,以避免 通过米勒效应减少主开关晶体管(102)的无意导通。

    METHOD AND APPARATUS FOR REDUCING LOCAL OSCILLATOR LEAKAGE IN INTEGRATED CIRCUIT RECEIVERS
    2.
    发明申请
    METHOD AND APPARATUS FOR REDUCING LOCAL OSCILLATOR LEAKAGE IN INTEGRATED CIRCUIT RECEIVERS 审中-公开
    减少集成电路接收机中局部振荡器漏电的方法和装置

    公开(公告)号:WO1994016502A1

    公开(公告)日:1994-07-21

    申请号:PCT/US1994000389

    申请日:1994-01-12

    Abstract: Technique for reducing local oscillator leakage in integrated frequency conversion circuits. The technique includes the step of coupling an external portion (35) of a resonator circuit (31, 35) to the integrated frequency conversion circuit (200). The coupling is accomplished without using any of the DC power or ground pins of the conversion circuit. A frequency conversion circuit based on this technique includes resonator, oscillator, and mixer circuits. Part of the oscillator and mixer circuit (16, 13) is encapsulated in a package (200), whereas at least a portion of the resonator circuit (35) is located outside the package. The outside portion of the resonator circuit (35) connects to at least two external resonator pins (43a, 43b) of the package (200) such that, during the operating of the conversion circuit, the net current entering the package via said external resonator pins (43a, 43b) is approximately zero.

    Abstract translation: 降低集成频率转换电路中本地振荡器泄漏的技术。 该技术包括将谐振器电路(31,35)的外部部分(35)耦合到集成频率转换电路(200)的步骤。 在不使用转换电路的任何直流电源或接地引脚的情况下实现耦合。 基于该技术的变频电路包括谐振器,振荡器和混频器电路。 振荡器和混频器电路(16,13)的一部分被封装在封装(200)中,而谐振器电路(35)的至少一部分位于封装外部。 谐振器电路(35)的外部部分连接到封装(200)的至少两个外部谐振器引脚(43a,43b),使得在转换电路的操作期间,经由所述外部谐振器进入封装的净电流 引脚(43a,43b)大约为零。

    MOSFET WITH GATE PULL-DOWN
    7.
    发明申请
    MOSFET WITH GATE PULL-DOWN 审中-公开
    MOSFET与门极拉低

    公开(公告)号:WO2011079194A2

    公开(公告)日:2011-06-30

    申请号:PCT/US2010/061784

    申请日:2010-12-22

    CPC classification number: H03K17/165 H03K17/687

    Abstract: A pull-down MOSFET (110) is coupled between a drain and gate of a MOSFET main switch transistor (102) in a switching type DC-to-DC power converter. A gate of the pull-down MOSFET (110) is coupled to the drain of the main switch transistor (102) by a capacitor 118 and is connected to a source of the main switch transistor (102) by a resistor (120). The pull-down MOSFET (110) is operated by capacitive coupling to the voltage drop across the main switch transistor (102) and can be used to hold the gate of the main switch transistor (102) at or near its source potential to avoid or reduce unintentional turn-on of the main switch transistor (102) by the Miller effect.

    Abstract translation: 下拉MOSFET(110)耦合在开关型DC-DC电力转换器中的MOSFET主开关晶体管(102)的漏极和栅极之间。 下拉MOSFET(110)的栅极通过电容器118耦合到主开关晶体管(102)的漏极,并通过电阻器(120)连接到主开关晶体管(102)的源极。 下拉MOSFET(110)通过与主开关晶体管(102)上的电压降的电容耦合来操作,并且可以用于将主开关晶体管(102)的栅极保持在其源极电位处或其附近,以避免或 减少主开关晶体管(102)的无意的接通由米勒效应。

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