公开(公告)号：WO2010059296A1

公开(公告)日：2010-05-27

申请号：PCT/US2009/059052

申请日：2009-09-30

Applicant: SANDISK 3D LLC ,  MATAMIS, George ,  CHIEN, Henry ,  KAI, James, K. ,  ORIMOTO, Takashi ,  PURAYATH, Vinod, R. ,  PING, Er-Xuan ,  SCHEUERLEIN, Roy, E.

Inventor： MATAMIS, George ,  CHIEN, Henry ,  KAI, James, K. ,  ORIMOTO, Takashi ,  PURAYATH, Vinod, R. ,  PING, Er-Xuan ,  SCHEUERLEIN, Roy, E.

IPC: G11C16/02 ,  H01L21/822 ,  H01L27/06 ,  H01L27/24

CPC classification number: H01L21/20 ,  G11C13/0004 ,  G11C17/16 ,  G11C2213/71 ,  G11C2213/72 ,  H01L27/101 ,  H01L27/1021 ,  H01L27/2409 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/06 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1675

Abstract: A self-aligned fabrication process for three-dimensional non-volatile memory is disclosed. A double etch process forms conductors at a given level in self-alignment with memory pillars both underlying and overlying the conductors. Forming the conductors in this manner can include etching a first conductor layer using a first repeating pattern in a given direction to form a first portion of the conductors. Etching with the first pattern also defines two opposing sidewalls of an underlying pillar structure, thereby self-aligning the conductors with the pillars. After etching, a second conductor layer is deposited followed by a semiconductor layer stack. Etching with a second pattern that repeats in the same direction as the first pattern is performed, thereby forming a second portion of the conductors that is self-aligned with overlying layer stack lines. These layer stack lines are then etched orthogonally to define a second set of pillars overlying the conductors.

Abstract translation: 公开了一种用于三维非易失性存储器的自对准制造工艺。 双重蚀刻工艺在与导体下面和上面的记忆柱自对准的给定水平处形成导体。 以这种方式形成导体可以包括使用沿给定方向的第一重复图案蚀刻第一导体层以形成导体的第一部分。 具有第一图案的蚀刻还限定了下面的柱结构的两个相对的侧壁，从而使导体与支柱自对准。 蚀刻后，沉积第二导体层，随后沉积半导体层堆叠。 执行以与第一图案相同的方向重复的第二图案的蚀刻，从而形成与上层叠层线自对准的导体的第二部分。 然后将这些层堆叠线正交蚀刻以限定覆盖导体的第二组支柱。

公开(公告)号：WO2013012682A3

公开(公告)日：2013-04-04

申请号：PCT/US2012046490

申请日：2012-07-12

Applicant: SANDISK TECHNOLOGIES INC ,  PURAYATH VINOD R ,  KAI JAMES K ,  PACHAMUTHU JAYAVEL ,  LIANG JARRETT JUN ,  MATAMIS GEORGE ,  HONMA RYOICHI

Inventor： PURAYATH VINOD R ,  KAI JAMES K ,  PACHAMUTHU JAYAVEL ,  LIANG JARRETT JUN ,  MATAMIS GEORGE ,  HONMA RYOICHI

IPC: H01L21/768 ,  H01L23/532

CPC classification number: H01L23/53238 ,  H01L21/7682 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76882 ,  H01L21/76885 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device including a plurality of copper interconnects. At least a first portion of the plurality of copper interconnects has a meniscus in a top surface. The semiconductor device also includes a plurality of air gaps, wherein each air gap of the plurality of air gaps is located between an adjacent pair of at least the first portion of the plurality of bit lines.

Abstract translation: 包括多个铜互连的半导体器件。 多个铜互连的至少第一部分在顶面具有弯液面。 半导体器件还包括多个气隙，其中多个气隙中的每个气隙位于多个位线的至少第一部分的相邻对之间。

公开(公告)号：WO2010005878A1

公开(公告)日：2010-01-14

申请号：PCT/US2009/049620

申请日：2009-07-02

Applicant: SANDISK CORPORATION ,  LEE, Dana ,  CHIN, Henry ,  KAI, James ,  ORIMOTO, Takashi, Whitney ,  PURAYATH, Vinod, R. ,  MATAMIS, George

Inventor： LEE, Dana ,  CHIN, Henry ,  KAI, James ,  ORIMOTO, Takashi, Whitney ,  PURAYATH, Vinod, R. ,  MATAMIS, George

IPC: H01L21/28 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L21/265

CPC classification number: H01L27/115 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/42324

Abstract: A memory system is disclosed that includes a set of non-volatile storage elements. A given memory cell has a dielectric cap above the floating gate. In one embodiment, the dielectric cap resides between the floating gate and a conformal IPD layer. The dielectric cap reduces the leakage current between the floating gate and a control gate. The dielectric cap achieves this reduction by reducing the strength of the electric field at the top of the floating gate, which is where the electric field would be strongest without the dielectric cap for a floating gate having a narrow stem.

Abstract translation: 公开了一种包括一组非易失性存储元件的存储器系统。 给定的存储单元在浮动栅极上方具有电介质盖。 在一个实施例中，电介质帽位于浮动栅极和共形IPD层之间。 电介质盖减少了浮动栅极和控制栅极之间的漏电流。 电介质盖通过降低浮动栅极顶部的电场的强度来实现这种减小，这是电场将是最强的，而没有用于具有窄的杆的浮动栅极的电介质盖。

公开(公告)号：WO2013012682A2

公开(公告)日：2013-01-24

申请号：PCT/US2012/046490

申请日：2012-07-12

Applicant: SANDISK TECHNOLOGIES INC. ,  PURAYATH, Vinod R. ,  KAI, James K. ,  PACHAMUTHU, Jayavel ,  LIANG, Jarrett Jun ,  MATAMIS, George ,  HONMA, Ryoichi

Inventor： PURAYATH, Vinod R. ,  KAI, James K. ,  PACHAMUTHU, Jayavel ,  LIANG, Jarrett Jun ,  MATAMIS, George ,  HONMA, Ryoichi

IPC: H01L21/768 ,  H01L23/532

CPC classification number: H01L23/53238 ,  H01L21/7682 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76882 ,  H01L21/76885 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device including a plurality of copper interconnects. At least a first portion of the plurality of copper interconnects has a meniscus in a top surface. The semiconductor device also includes a plurality of air gaps, wherein each air gap of the plurality of air gaps is located between an adjacent pair of at least the first portion of the plurality of bit lines.

Abstract translation: 包括多个铜互连的半导体器件。 多个铜互连的至少第一部分在顶面中具有弯月面。 所述半导体器件还包括多个气隙，其中所述多个气隙中的每个气隙位于所述多个位线的至少所述第一部分的相邻对之间。

公开(公告)号：WO2009129053A1

公开(公告)日：2009-10-22

申请号：PCT/US2009/039202

申请日：2009-04-01

Applicant: SANDISK CORPORATION ,  CHIEN, Henry ,  PURAYATH, Vinod, R. ,  KAI, James ,  MATAMIS, George ,  ORIMOTO, Takashi

Inventor： CHIEN, Henry ,  PURAYATH, Vinod, R. ,  KAI, James ,  MATAMIS, George ,  ORIMOTO, Takashi

IPC: G11C11/56 ,  G11C11/16

CPC classification number: G11C8/10 ,  G11C8/04 ,  G11C11/5621 ,  G11C16/0483 ,  G11C19/00 ,  H01L21/28273 ,  H01L27/11521

Abstract: A non-volatile storage system in which a sidewall insulating layer of a floating gate is significantly thinner than a thickness of a bottom insulating layer, and in which raised source/drain regions are provided. During programming or erasing, tunneling occurs predominantly via the sidewall insulating layer and the raised source/drain regions instead of via the bottom insulating layer. The floating gate may have a uniform width or an inverted T shape. The raised source/drain regions may be epitaxially grown from the substrate, and may include a doped region above an undoped region so that the channel length is effectively extended from beneath the floating gate and up into the undoped regions, so that short channel effects are reduced. The ratio of the thicknesses of the sidewall insulating layer to the bottom insulating layer may be about 0.3 to 0.67.

Abstract translation: 一种非易失性存储系统，其中浮动栅极的侧壁绝缘层比底部绝缘层的厚度明显薄，并且其中设置有凸起的源极/漏极区域。 在编程或擦除期间，隧道主要通过侧壁绝缘层和凸起的源极/漏极区域而不是通过底部绝缘层发生。 浮动门可以具有均匀的宽度或倒T形。 凸起的源极/漏极区域可以从衬底外延生长，并且可以包括在未掺杂区域上方的掺杂区域，使得沟道长度从浮置栅极下方有效地延伸并且向上延伸到未掺杂区域，使得短沟道效应为 降低。 侧壁绝缘层与底部绝缘层的厚度的比可以为约0.3〜0.67。