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    APPARATUSES INCLUDING STAIR-STEP STRUCTURES AND METHODS OF FORMING THE SAME
    1.
    发明申请
    APPARATUSES INCLUDING STAIR-STEP STRUCTURES AND METHODS OF FORMING THE SAME 审中-公开
    装置包括平台结构及其形成方法

    公开(公告)号：WO2012166483A3

    公开(公告)日：2013-03-07

    申请号：PCT/US2012039215

    申请日：2012-05-23

    Applicant: MICRON TECHNOLOGY INC ,  FREEMAN ERIC H ,  SMITH MICHAEL A

    Inventor： FREEMAN ERIC H ,  SMITH MICHAEL A

    IPC: H01L21/8247 ,  H01L27/115

    CPC classification number: H01L23/528 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/32133 ,  H01L21/32139 ,  H01L21/76838 ,  H01L21/76892 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11575 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Methods for forming semiconductor structures are disclosed, including a method that involves forming sets of conductive material and insulating material, forming a first mask over the sets, forming a first number of contact regions, forming a second mask over a first region of the sets, and removing material from of the sets in a second, exposed region laterally adjacent the first region to form a second number of contact regions. Another method includes forming first and second contact regions on portions of sets of conductive materials and insulating materials, each of the second contact regions more proximal to an underlying substrate than each of the first contact regions. Apparatuses such as memory devices including laterally adjacent first and second regions each including contact regions of a different portion of a plurality of conductive materials and related methods of forming such devices are also disclosed.

    Abstract translation: 公开了用于形成半导体结构的方法，包括形成导电材料和绝缘材料组的方法，在组上形成第一掩模，形成第一数量的接触区域，在组的第一区域上形成第二掩模， 以及在与所述第一区域横向相邻的第二暴露区域中从所述组中移除材料以形成第二数量的接触区域。 另一种方法包括在导电材料和绝缘材料组的部分上形成第一和第二接触区域，每个第二接触区域比第一接触区域中的每一个更接近下面的衬底。 还公开了诸如包括横向相邻的第一和第二区域的存储器件的装置，每个区域包括多个导电材料的不同部分的接触区域和形成这种器件的相关方法。

    STYRENE BUTADIENE BLOCK COPOLYMERS FOR FILM APPLICATIONS
    7.
    发明申请
    STYRENE BUTADIENE BLOCK COPOLYMERS FOR FILM APPLICATIONS 审中-公开
    苯乙烯丁二烯嵌段共聚物的薄膜应用

    公开(公告)号：WO2008073932A1

    公开(公告)日：2008-06-19

    申请号：PCT/US2007/087063

    申请日：2007-12-11

    Applicant: CHEVRON PHILLIPS CHEMICAL COMPANY LP ,  BROWN, John M. ,  SMITH, Michael A. ,  STACY, Nathan E. ,  STOUFFER, Carleton E ,  WILKEY, John D

    Inventor： BROWN, John M. ,  SMITH, Michael A. ,  STACY, Nathan E. ,  STOUFFER, Carleton E ,  WILKEY, John D

    IPC: C08F297/04 ,  C08L53/02

    CPC classification number: C08J5/18 ,  C08F212/08 ,  C08F297/04 ,  C08F297/044 ,  C08F301/00 ,  C08J2325/10 ,  C08J2347/00 ,  C08J2425/06 ,  C08L53/02 ,  C08L2666/02 ,  C08L2666/04

    Abstract: We disclose a monovinylarene-conjugated diene block copolymer containing a plurality of monovinylarene-conjugated diene mixed blocks, wherein each mixed block contains conjugated diene units and monovinylarene units in a weight ratio of about 0.05 to about 0.33. We also disclose a composition containing (a) from about 50 parts by weight to about 95 parts by weight of the monovinylarene-conjugated diene block copolymer and (b) from about 5 parts by weight to about 50 parts by weight of polystyrene; wherein the monovinylarene-conjugated diene block copolymer and the polystyrene total 100 parts by weight. We further disclose a method of shrink-wrapping an object or a group of objects by wrapping the object or the group of objects with a film containing the composition, to yield a wrapped object or group of objects, and heating the wrapped object or group of objects to a temperature and for a duration sufficient to shrink the film in at least a first direction, to yield a shrink-wrapped object or group of objects.

    Abstract translation: 我们公开了含有多个单乙烯基芳烃 - 共轭二烯混合嵌段的单乙烯基芳烃 - 共轭二烯嵌段共聚物，其中每个混合嵌段含有约0.05-约0.33重量比的共轭二烯单元和单乙烯基芳烃单元。 我们还公开了一种组合物，其包含（a）约50重量份至约95重量份的单乙烯基芳烃 - 共轭二烯嵌段共聚物和（b）约5重量份至约50重量份的聚苯乙烯; 其中单乙烯基芳烃 - 共轭二烯嵌段共聚物和聚苯乙烯共计100重量份。 我们进一步公开了一种通过用包含该组合物的胶片包裹物体或一组物体来收缩包裹物体或一组物体的方法，以产生包裹的物体或物体组，并加热包裹的物体或组 对象达到足以在至少第一方向上收缩膜的温度和持续时间，以产生收缩包裹的物体或物体组。

    RETAIL LENDING RISK RELATED SCENARIO GENERATION
    8.
    发明申请
    RETAIL LENDING RISK RELATED SCENARIO GENERATION 审中-公开

    公开(公告)号：WO2003067395A3

    公开(公告)日：2003-08-14

    申请号：PCT/US2003/003677

    申请日：2003-02-07

    Applicant: STRATEGIC ANALYTICS INC. ,  BREEDEN, Joseph, L. ,  SMITH, Michael, A. ,  FRANKLIN, R., David

    Inventor： BREEDEN, Joseph, L. ,  SMITH, Michael, A. ,  FRANKLIN, R., David

    IPC: G06F17/60

    Abstract: Generation of risk-related retail lending portfolio scenarios is disclosed. A selected functional form is used to decompose vintage performance data into a maturation component (200), and exogenous component (210) and vintage calibration parameters (212) for the portfolio. Known exogenous drivers are extracted from the exogenous component (210) to create a residual exogenous component. Monthly changes in the residual exogenous component are computed, and the distribution of monthly changes in the residual exogenous component is measured. This information is used to generate a number of random potential future scenarios for the residual exogenous component and, ultimately, for the generation of a number of forecasts for key portfolio drivers.

    CONDUCTIVE STRUCTURES, SYSTEMS AND DEVICES INCLUDING CONDUCTIVE STRUCTURES AND RELATED METHODS
    9.
    发明申请
    CONDUCTIVE STRUCTURES, SYSTEMS AND DEVICES INCLUDING CONDUCTIVE STRUCTURES AND RELATED METHODS 审中-公开
    导电结构，系统和装置，包括导电结构和相关方法

    公开(公告)号：WO2012166451A3

    公开(公告)日：2013-02-28

    申请号：PCT/US2012039042

    申请日：2012-05-23

    Applicant: MICRON TECHNOLOGY INC ,  SMITH MICHAEL A ,  FREEMAN ERIC H

    Inventor： SMITH MICHAEL A ,  FREEMAN ERIC H

    IPC: H01L21/8247 ,  H01L21/28 ,  H01L27/115

    CPC classification number: H01L23/5226 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76877 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11575 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Conductive structures include a plurality of conductive steps and a contact extending at least partially therethrough in communication with at least one of the plurality of conductive steps and insulated from at least another one of the conductive steps. Devices may include such conductive structures. Systems may include a semiconductor device and a stair step conductive structure having a plurality of contacts extending through a step of the stair step conductive structure. Methods of forming conductive structures include forming contacts in contact holes formed through at least one conductive step of a conductive structure. Methods of forming electrical connections in stair step conductive structures include forming contacts in contact holes formed through each step of the stair step conductive structure.

    Abstract translation: 导电结构包括多个导电台阶和至少部分地穿过其延伸的接触件，与多个导电台阶中的至少一个连通，并与至少另一导电台阶绝缘。 设备可以包括这种导电结构。 系统可以包括半导体器件和楼梯级导电结构，其具有延伸穿过楼梯级导电结构的台阶的多个触点。 形成导电结构的方法包括在通过导电结构的至少一个导电步骤形成的接触孔中形成接触。 在楼梯级导电结构中形成电连接的方法包括在通过楼梯级导电结构的每个步骤形成的接触孔中形成触点。

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