公开(公告)号：WO1995026122A1

公开(公告)日：1995-09-28

申请号：PCT/CH1994000062

申请日：1994-03-23

Applicant: DYCONEX PATENTE AG ,  MARTINELLI, Marco ,  SCHMIDT, Walter

Inventor： DYCONEX PATENTE AG

IPC: H05K03/00

CPC classification number: H05K3/4697 ,  H05K1/028 ,  H05K3/0041 ,  H05K3/4652 ,  H05K2201/0191 ,  H05K2203/0554 ,  H05K2203/0557 ,  H05K2203/1184

Abstract: The invention concerns a multi-layer foil printed circuit board which comprises rigid areas (s) and flexible areas (f) and has more foil layers in the rigid areas than in the flexible areas. The foil printed circuit board is produced by removal of at least the outermost foil layer (1.2) or reduction of its thickness by etching at least on one side in the flexible areas (f) provided. By appropriate configuration of the etching mask, the flexible areas (f) can be made to merge continuously into rigid areas (s) as a result of less material being removed from the layers in the edge areas (u) than in the centre (z) of the flexible area (f), so that the flexible areas do not have any edge areas tending to kink. The flexible areas can be etched in the same step as the etching of the through-plating holes in the corresponding foil layer (1.2) or in a separating etching step.

Abstract translation: 根据本发明的，多层薄膜电路板具有刚性的（一个或多个）和柔性的（F）部分，其中它包括在所述刚性区域Fohlinlagen比在柔性区域更多。 本发明的膜的电路板是由在至少一侧产生是至少最箔层（1.2）中除去或通过在厚度减小蚀刻在所提供的柔性区域（F）。 通过蚀刻掩模的适当的配置，可能的是，柔性区域（F）连续地在刚性区域（一个或多个）与过渡，其特征在于去除在边缘区域中的帘布层（U）的小于所述柔性区域的中心（Z）（ F），从而形成屈曲柔性部分的边缘区域没有倾向。 柔性部分的蚀刻可以在相同的工艺步骤的通孔通过各自的箔片层（1.2）蚀刻或在单独的蚀刻步骤来执行。

公开(公告)号：WO1995002312A1

公开(公告)日：1995-01-19

申请号：PCT/CH1994000134

申请日：1994-06-24

Applicant: DYCONEX PATENTE AG ,  MARTINELLI, Marco ,  SCHMIDT, Walter

Inventor： DYCONEX PATENTE AG

IPC: H05K03/00

CPC classification number: H05K3/428 ,  H05K1/0393 ,  H05K3/0041 ,  H05K3/28 ,  H05K2203/0554 ,  H05K2203/0557 ,  H05K2203/0574 ,  Y10T29/49126 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: The invention relates to multi-layer printed circuit boards, film printed circuit boards and semi-finished products for printed circuit films and a process for their production, with through-plating (12) structured in insulator layers (2), structured apertures (4, 4') in cover layers (A, A') of the surfaces (O, O'), current tracks (SP) structured in conductive layers and contact points (K, K'). To reduce the number of photochemical structuration operations required, the through-plating (12) and the cover apertures (4, 4') are mechanically structured in that pre-formed through-plating apertures (10, 10') are etched in insulating layers (2) in accordance with through-plating structures (8, 8') of masking films (7, 7'), electrically conductive substances are deposited in the through-plating apertures (10, 10') to form contact layers (11) in said through-plating apertures (10) and apertures (4, 4') are etched in accordance with contact structures (3, 3') of masking films (7, 7') in cover layers (A, A') in such a way that the apertures (4, 4') form cover-material-free regions on the printed circuit boards and film printed circuit boards and on the semi-finished products for such printed circuit boards and the apertures (4, 4') are freely shaped so as to be cylindrical, round, oval, square, rectangular or polygonal.

Abstract translation: 本发明涉及多层印刷电路板，金属箔的电路板和半成品为箔的电路板和用于生产其的方法，具有结构化在绝缘体层（2）的界面连接（12），在覆盖层的表面的（A，A“）的结构覆盖开口（4，4”）（ O，O“），在导体层构成的电流路径（SP），（与接触点K，K”），由此减少所需的光化学结构的数目的界面连接（12）和所述覆盖开口（4，4“）在机械结构 通过在绝缘体层（2） '根据Durchplattierungsstrukturen（8,8掩模箔）（7，7'）预处理Durchplattierungsöffnungen（10，10） '被蚀刻，即在Durchplattierungsöffnungen（10，10'）的导电Abscheidesubstanzen以形成 在Durchplattierungsöffnungen接触层（11）（10）通过并在覆盖层（A，A '）覆盖的开口（4，4'）中分离 根据“（以这样的方式被蚀刻掩模箔7,7）的接触结构（3,3）”的是，覆盖开口（4，4“）上的电路板，箔电路板和在半成品这种箔的电路板形式abdeckmaterialfreie区域和覆盖开口（4， 包括4“）的工作自由形成的，圆筒形，圆形，椭圆形和正方形，矩形，多边形的直径。

公开(公告)号：WO1993026143A1

公开(公告)日：1993-12-23

申请号：PCT/CH1993000145

申请日：1993-06-09

Applicant: DYCONEX PATENTE AG ,  SCHMIDT, Walter ,  MARTINELLI, Marco

Inventor： DYCONEX PATENTE AG

IPC: H05K03/00

CPC classification number: H05K3/4655 ,  H05K1/0287 ,  H05K1/0289 ,  H05K1/0393 ,  H05K1/05 ,  H05K1/115 ,  H05K3/0041 ,  H05K3/0061 ,  H05K3/0064 ,  H05K3/0097 ,  H05K3/386 ,  H05K3/4084 ,  H05K3/42 ,  H05K3/427 ,  H05K3/429 ,  H05K3/4635 ,  H05K3/4641 ,  H05K3/4652 ,  H05K2201/0195 ,  H05K2201/0355 ,  H05K2201/0394 ,  H05K2201/0397 ,  H05K2201/066 ,  H05K2201/0909 ,  H05K2201/09327 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/09554 ,  H05K2201/09572 ,  H05K2201/09609 ,  H05K2201/09627 ,  H05K2201/09781 ,  H05K2201/09836 ,  H05K2201/09945 ,  H05K2201/10666 ,  H05K2203/0554 ,  H05K2203/0746 ,  H05K2203/1184 ,  H05K2203/1545 ,  H05K2203/1572 ,  Y10S428/901 ,  Y10T428/24917

Abstract: The initial intention in the semi-finished product of the invention is to provide a functional separation between the requirement for mechanical strength and the previously concomitant requirement, for completing a circuit, in order to bring the pure circuit connection, especially for signals, "closer" to the electrical and technical properties of chips. To do this, the layout miniaturisation is optimised without regard for the mechanical strength of the substrate. Instead of a printed circuit board (MCM), a semi-finished product which can be developed into a printed circuit board is made. The semi-finished product of the invention consists of an extremely thin film (8) with a plurality of extremely small holes (14) made simultaneously by an etching process. The hole diameters can be reduced by almost an order of magnitude (down to 20 mu m), facilitating, for instance, definite sub-100 mu m technology. Such a semi-finished product (19) does not act as a mechanical support but is designed only for signal conduction. The semi-finished product (19) which carries the densely packed wiring pattern, is bonded to a not densely packed power supply plane (22) acting as the service plane and the printed circuit board thus made is finally secured to a mechanical support (20).

公开(公告)号：WO1995026123A1

公开(公告)日：1995-09-28

申请号：PCT/CH1994000063

申请日：1994-03-23

Applicant: DYCONEX PATENTE AG ,  MARTINELLI, Marco ,  SCHMIDT, Walter

Inventor： DYCONEX PATENTE AG

IPC: H05K03/00

CPC classification number: H05K3/0041 ,  H05K1/0393 ,  H05K3/0052 ,  H05K3/007 ,  H05K3/0097 ,  H05K3/4652 ,  H05K2201/09036 ,  H05K2201/09063 ,  H05K2201/0909 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2203/0156 ,  H05K2203/0191 ,  H05K2203/0554 ,  H05K2203/1545

Abstract: Foil printed circuit boards or semi-finished products for foil printed circuit boards are produced from virtually continuous foil material. The individual units produced remain interconnected by predetermined folding points so that they can be processed in the form of a folded length of material and permanently or temporarily stored in the form of a folded stack. Pieces of foil material can also exist in the form of folded lengths as a result of the fact that the individual units are interconnected in a foldable manner by flexible connections. The predetermined folding points (SK) in the almost continuous foil material comprising one or more foil layers (1.1, 1.2, 1.3) are produced by locally weakened points in the material, consisting of interruptions or reductions in the thickness of at least one of the foil layers (1.2). These weakened points are produced in the same etching steps in which perforated structures (3, 4, 5, 6) for particular functions are produced.

Abstract translation: 准环形膜材料箔的电路板或半成品的是为箔电路板制造，与个体，制造单位保持经由弱化线彼此连接，使得它们可以以Faltwurmes的形式被处理并存储在一个折叠堆的形式，或者暂时存储。 此外，在货物Faltwurm的形式的膜材料可以通过各个单元与柔性连接件可折叠地彼此连接来形成。 由一个或多个箔层（1.1，1.2，1.3）的组中的预先确定的弯曲点（SK），准循环胶片材料通过由中断或箔片层中的至少一个（1.2）的厚度的减少削弱本地材料制成。 这些弱化在其中与功能相关的孔结构（3，4，5，6）中产生相同的蚀刻步骤制造。

公开(公告)号：WO1993026144A1

公开(公告)日：1993-12-23

申请号：PCT/CH1993000147

申请日：1993-06-10

Applicant: DYCONEX PATENTE AG ,  SCHMIDT, Walter ,  MARTINELLI, Marco

Inventor： DYCONEX PATENTE AG

IPC: H05K03/40

CPC classification number: H05K3/4084 ,  H05K1/0287 ,  H05K1/0289 ,  H05K1/0393 ,  H05K1/05 ,  H05K1/115 ,  H05K3/0041 ,  H05K3/0061 ,  H05K3/0064 ,  H05K3/0097 ,  H05K3/386 ,  H05K3/427 ,  H05K3/429 ,  H05K3/4652 ,  H05K2201/0195 ,  H05K2201/0355 ,  H05K2201/0394 ,  H05K2201/0397 ,  H05K2201/066 ,  H05K2201/0909 ,  H05K2201/09327 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/09554 ,  H05K2201/09609 ,  H05K2201/09627 ,  H05K2201/09781 ,  H05K2201/09836 ,  H05K2201/09945 ,  H05K2201/10666 ,  H05K2203/0554 ,  H05K2203/0746 ,  H05K2203/1184 ,  H05K2203/1545 ,  H05K2203/1572

Abstract: The process for producing subsequently contactable contact points between two conductive track planes on a circuit substrate separated by an electrically insulating layer makes it possible to produce, for example, a basic conductor pattern which can subsequently be easily adapted to requirements. By laying windows in the conductive track planes out in such a way that, when the electrically insulating layer is subsequently through-etched due to under-etching, rod-like parts connected to the aperture periphery are revealed between or in the apertures which can be brought into contact with electrically conductive parts of the other conductive track plane, these conductive tracks can be electrically interconnected by mechanical bending.

公开(公告)号：WO1995031883A1

公开(公告)日：1995-11-23

申请号：PCT/CH1994000092

申请日：1994-05-18

Applicant: DYCONEX PATENTE AG ,  SCHMIDT, Walter ,  MARTINELLI, Marco

Inventor： DYCONEX PATENTE AG

IPC: H05K03/00

CPC classification number: H05K3/403 ,  H01L21/4857 ,  H01L23/5387 ,  H01L2924/0002 ,  H05K1/0218 ,  H05K1/0393 ,  H05K1/118 ,  H05K3/0041 ,  H05K3/0052 ,  H05K3/3442 ,  H05K3/363 ,  H05K3/427 ,  H05K3/428 ,  H05K3/4652 ,  H05K2201/09063 ,  H05K2201/09081 ,  H05K2201/0909 ,  H05K2201/09172 ,  H05K2203/0554 ,  H05K2203/0557 ,  Y10T29/49121 ,  Y10T29/49171 ,  Y10T428/24917 ,  H01L2924/00

Abstract: A process is disclosed for manufacturing printed circuit boards, printed circuit foils and semifinished products for printed circuit boards and printed circuit foils from blanks with electroconductive layers (7, 8) that may be structured into conductive patterns and substrates (4) that may be structured for forming connecting means (V), profiles (K) and conductive patterns (L). The connecting means (V), profiles (K) and conductive patterns (L) are structured at the same time or in the same process steps on the blanks. The connecting means (V) and the profiles (K) are part of the structured substrate (4) of the blanks. The electric or mechanical connecting means (V) are placed in a position in which they may be connected and the finished conductive patterns (L) may be detached around the profiles (K).

Abstract translation: 本发明涉及一种用于生产印刷电路板，金属箔的电路板和半成品用于电路板和薄膜电路板由前体与结构化到导电图案的导电层（7，8）和可以是结构化的基板（4），用于轮廓的连接装置（V）的形成 （K），以及布线图案（L），其中，所述连接装置（V），轮廓（K）和布线图案（L）是在同一时刻或在所述前体的相同的处理步骤，并且所述连接装置（V）和轮廓（K）的所述部分图案化 织构的衬底（4）中，前体是，被带到用于在位置上的电或机械连接的连接装置（V）在它们所连接，并且完成了印刷电路的图像（L）上的轮廓（K）是可拆卸的。

公开(公告)号：WO1995021517A1

公开(公告)日：1995-08-10

申请号：PCT/CH1995000022

申请日：1995-02-01

Applicant: DYCONEX PATENTE AG ,  SCHMIDT, Walter ,  MARTINELLI, Marco

Inventor： DYCONEX PATENTE AG

IPC: H05K03/00

CPC classification number: H05K3/0041 ,  H05K3/143 ,  H05K3/184 ,  H05K3/426 ,  H05K3/428 ,  H05K2201/09509 ,  H05K2203/0542 ,  H05K2203/0554 ,  H05K2203/1142

Abstract: In the process of the invention for the production of multi-layer film printed circuit boards from semi-finished products (A), with current paths (B) structured in electrically conductive layers (1, 3) and with electrically conductive plating (C, D) from conductive layer (1) to conductive layer (3) through an insulating layer (2), or for the production of semi-finished items for such foil printed circuit boards, in initial steps in the process a structuring agent (7, 7', 13) is applied in a controlled fashion locally to the semi-finished item (A) and cover layers (8, 9) are applied to the surface of the semi-finished item (A). The structuring agent (7, 7', 13) is either applied to the cover layers (8, 9) which are then locally removed or the cover layers (8, 9) are applied to structuring agents (7, 7', 13) and in a further step the structuring agent (7, 7', 13) applied is removed leaving apertures (10, 10') in the cover layers (8, 9) extending as far as the insulating layer (2). In a further step, through or blind holes (11, 11') are locally etched into the insulating layer (2) at the location of the appertures (10, 10') and, to produce electrically conductive plating (C, D), electrically conductive deposition substances (12) are deposited in the through or blind holes (11, 11').

Abstract translation: 在用于生产Vorfabrikaten（A）的多层薄膜电路板的新方法，与在导电性层（1,3）构成的电流路径（B），并用由绝缘体层中的导电层的导电性的金属镀层（C，D）（1）与导电层（3） （2），或为半成品用于这种箔的电路板，一个结构的装置（7,7”，13）在第一方法步骤和局部的预制组分（a）和抗蚀剂施加的涂层（8,9）平贴在预制组分（a）进行控制的制造 其中，所述结构的装置（7,7”，13）无论是在抗蚀剂涂层（8,9）施加和覆盖层（8,9）局部地除去或者该覆盖层（8,9）的结构的装置（7，7' ， 13）可以被应用，将在另外的方法步骤中，施加的结构的装置（7，7“被除去，13），使得开口（10，10”）（在包覆层8，9）形成，所述绝缘层（ 2）雏 Breichen，在通过进一步的处理步骤或盲孔“在开口的位置（10，10）（11 11）”局部绝缘层中蚀刻（2）和用于产生导电性的金属镀层（C，D）是导电 Abscheidesubstanzen（12）在通或盲孔（11，11“）被沉积。

公开(公告)号：WO1993026146A1

公开(公告)日：1993-12-23

申请号：PCT/CH1993000148

申请日：1993-06-10

Applicant: DYCONEX PATENTE AG ,  SCHMIDT, Walter ,  MARTINELLI, Marco

Inventor： DYCONEX PATENTE AG

IPC: H05K07/20

CPC classification number: H05K7/205 ,  H05K1/0206 ,  H05K1/0287 ,  H05K1/0289 ,  H05K1/0393 ,  H05K1/05 ,  H05K1/115 ,  H05K3/0041 ,  H05K3/0061 ,  H05K3/0064 ,  H05K3/0097 ,  H05K3/386 ,  H05K3/427 ,  H05K3/429 ,  H05K3/4652 ,  H05K2201/0195 ,  H05K2201/0355 ,  H05K2201/0394 ,  H05K2201/0397 ,  H05K2201/066 ,  H05K2201/0909 ,  H05K2201/09327 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/09554 ,  H05K2201/09572 ,  H05K2201/09609 ,  H05K2201/09627 ,  H05K2201/09781 ,  H05K2201/09836 ,  H05K2201/09945 ,  H05K2201/10666 ,  H05K2203/0554 ,  H05K2203/0746 ,  H05K2203/1184 ,  H05K2203/1545 ,  H05K2203/1572

Abstract: According to a process for producing a thermal layout, not only massive heat sinks are provided for absorbing heat, but also an optimized number of thermoconductive strips which distribute the heat over the printed circuit board. In the collecting zones are arranged higher capacity sinks into which the heat is transmitted. The thermoconductive strips may be thermoconductors (TL) provided for that purpose and more massive than the conductive strips for the electric connections, or conductive strips for electric connections, the electroconductors (EL), may also be used for heat transfer. An optimum design interconnects the TL'S and EL's into a functional whole, a thermal management network. With a certain technique, which could be called pocket groove technique, "cooling channels" of a type may be created. Such thermoconductors may be included in the electric layout, so that a thermal layout is superimposed on the connection layout (TL/EL network). Heat distribution and transfer may thus be calculated and optimized by a computer in the same way as the electric distribution by the conductive strips, i.e. the known electric layout, which is produced by a computer-assisted process.

公开(公告)号：WO1997018695A1

公开(公告)日：1997-05-22

申请号：PCT/CH1996000394

申请日：1996-11-06

Applicant: DYCONEX PATENTE AG ,  SCHMIDT, Walter

Inventor： DYCONEX PATENTE AG

IPC: H05K03/46

CPC classification number: H05K3/4655 ,  H05K3/0097 ,  H05K3/025 ,  H05K3/4652 ,  H05K3/4676 ,  H05K2201/0195 ,  H05K2201/0355 ,  H05K2201/0358 ,  H05K2203/1536

Abstract: The invention relates to a process for making printed circuit boards from semi-finished foil products (F.2/6/6'/6") in which at least two semi-finished foil products (F.2/6/6'/6") are bonded together under pressure and temperature via at least two viscous insulating layers (2, 7) which are physically different from each other in that one insulating layer (7) does not melt to liquid form and acts as a spacer, the other insulating layer (2) melts to liquid form during bonding and acts as a bonding agent, a bonding semi-finished foil product (F.2/6/6'/6") with insulating layers (2, 7) is used therefor and spacing insulating layers (7) are applied to conductive layers (1) and bonding insulating layers (2) are applied to spacing insulating layers (7).

Abstract translation: 本发明涉及一种用于制造印刷电路板的从半成品箔制品（F.2 / 6/6的方法“/ 6），其中至少两个膜的半成品（F.2 / 6/6” / 6）一起压力和温度的至少两个下粘性 绝缘层（2,7）连接，其由绝缘体层物理上彼此不同（7）不会熔化连接并充当间隔装置期间流动，即（2）的其它绝缘体层中流动连接期间熔化并用作连接装置，为了这个目的 连接半成品箔制品使用具有绝缘层（F.6 / 6“/ 6）（2，7），并且该空间保持绝缘层（7）被施加到导电层（1）和施加（7）上空间保持绝缘层连接绝缘体层（2） 是。

公开(公告)号：WO1997000598A1

公开(公告)日：1997-01-03

申请号：PCT/CH1996000218

申请日：1996-06-06

Applicant: DYCONEX PATENTE AG ,  ATOTECH DEUTSCHLAND GMBH ,  CIBA SC HOLDING AG ,  FRAUNHOFER-GESELLSCHAFT ZUR FÖRDERUNG DER ANGEWANDTEN FORSCHUNG E.V. ,  TECHNISCHE UNIVERSITÄT DRESDEN ,  BARTE, Hans-Jürg ,  LOSERT, Ewald ,  MEYER, Heinrich ,  RÖHRS, Günter ,  RUDOLF, Frank ,  SCHEEL, Wolfgang ,  SCHMIDT, Walter ,  ZUR NIEDEN, Theis

Inventor： DYCONEX PATENTE AG ,  ATOTECH DEUTSCHLAND GMBH ,  CIBA SC HOLDING AG ,  FRAUNHOFER-GESELLSCHAFT ZUR FÖRDERUNG DER ANGEWANDTEN FORSCHUNG E.V. ,  TECHNISCHE UNIVERSITÄT DRESDEN

IPC: H05K01/00

CPC classification number: H05K3/284 ,  H01L23/50 ,  H01L23/5385 ,  H01L25/065 ,  H01L25/162 ,  H01L2224/16225 ,  H05K1/0203 ,  H05K1/189 ,  H05K3/0058 ,  H05K2201/0209 ,  H05K2201/042 ,  H05K2201/046 ,  H05K2201/2009 ,  H05K2203/1316 ,  Y10S428/901 ,  Y10T29/49128 ,  Y10T29/49155

Abstract: The proposed method of producing multifunctional multilayered connection substrates involves the following: the connection substrate is built up function by function from the various components, i.e. signal conducting substrate components (19), power supply substrate components (2), thermal substrate components (20), mechanical substrate components (7), and the arrangement of the components (4) and component-bearing substrate components as interdependent functions or modules, are designed and optimised separately before finally being assigned to spatially separated functional areas (inner/outer) of the circuit. The construction process involves connecting the modules to a circuit which forms the connection substrate. The substrate components with fine, compact, flexible and cool elements are assigned to the inner areas of the circuit, while those substrate components with coarse, rigid and warm elements and/or components are assigned to the outer areas of the circuit; a stiffening support material is applied in the outer area in such a way as to give the circuit a mechanical support structure which is designed to have rigid sections which merge into flexible sections. The circuit can be folded and/or wound according to the rigid and flexible sections. The mechanical support structure can be formed by separately manufactured device housing components or by the device housing.

Abstract translation: 对于生产具有多种功能的多层互连衬底的方法，是使连接基板的功能的结构通过信号导电基底部件（19），stromversorgende基板份（2），热基底部件（20），机械基底部件（7），以及各部件的布置分开进行 （4）或支撑基板份组分分开规划为相互依赖的功能或单独优化模块和最后空间上分开的功能区域（内部/外部）由模块在连接到所述互连衬底体现整体电路中发生分配给整个电路，该结构。 基板的与细的，致密的，灵活的和冷却元件的片被分配给整个电路的内部区域，与粗，刚性和温暖的元件和/或与整个电路的外部区域相关联的部件，和一种硬化的载体材料的衬底部分是在外部区域 可以被设计，使得电路被赋予机械载体结构，所述载体结构被局部地在越过，总电路根据折叠和/或缠绕在刚性和柔性部分的设计刚性和柔性的区域。 机械支撑结构可以通过单独制造设备壳体部件或由装置壳体而形成。