摘要:
Techniques and mechanisms to provide interconnect structures of a substrate such as a printed circuit board. In an embodiment, a first side of a substrate has disposed thereon a hardware interface contacts to couple the substrate to a packaged IC device. The contacts define a footprint area, where an overlap region of the substrate is defined by a projection of the footprint area from the first side to a second side of the substrate. The substrate forms a recess extending from one of the first side and the second side. In another embodiment, at least part of the recess is within the overlap region, and interconnect structures of the substrate facilitate connection between the packaged IC device and a capacitor disposed at least partially in the recess. Positioning of the capacitor within the overlap region enables improvements in substrate space efficiency, power delivery and/or signal noise.
摘要:
A substrate that includes a first dielectric layer and a capacitor embedded in the first dielectric layer. The capacitor includes a first terminal, a second terminal, and a third terminal. The second terminal is laterally located between the first terminal and the third terminal. The capacitor also includes a second dielectric layer, a first metal layer and a second metal layer. The first metal layer is coupled to the first and third terminals. The first metal layer, the first terminal, and the third terminal are configured to provide a first electrical path for a first signal. The second metal layer is coupled to the second terminal. The second metal layer and the second terminal are configured to provide a second electrical path for a second signal.
摘要:
A connector device (600) for connection with a counter piece (1500) for establishing a mechanical and electric connection, wherein the connector device (600) comprises at least two printed circuit board elements (100) each comprising an electrically insulating core (102) and at least one comprising an electrically conductive structure (104) at least partially on the respective electrically insulating core (102), and at least one embedded component (106) embedded within the respective electrically insulating core (102) and electrically coupled to the respective electrically conductive structure (104), wherein the at least one electrically conductive structure (104) is arranged at least partially on an exposed surface of the connector device (600) and is configured for establishing the electric connection with the counter piece (1500) upon establishing the mechanical connection with the counter piece (1500).
摘要:
Ein Verfahren zum Ankontaktieren und Umverdrahten eines in eine Leiterplatte (2) eingebetteten elektronischen Bauteils (1) ist gekennzeichnet durch die folgenden Schritte: Auftragen einer ersten Permanentresistschicht (9) auf eine Kontaktseite (8) der Leiterplatte (2), Strukturieren der ersten Permanentresistschicht (11) zum Herstellen von Freistellungen (10, 12) im Bereich von Kontakten (7) des elektronischen Bauteils (1), Auftragen einer zweiten Permanentresistschicht (11) auf die strukturierte erste Permanentresistschicht (9), Strukturieren der zweiten Permanentresistschicht (11) zum Freilegen der Freistellungen (10) im Bereich der Kontakte (7) und zum Herstellen von Freistellungen (12) entsprechend den gewünschten Leiterzügen (15), Chemisches Beschichten der Freistellungen (10, 12) mit Kupfer, Galvanisches Auffüllen der Freistellungen (10, 12) mit Kupfer, Abtragen von Kupferüberschuss in den Bereichen zwischen den Freistellungen (10, 12).
摘要:
A semiconductor device package having reduced form factor and a method for forming said semiconductor device are disclosed. In an embodiment, an active die is embedded within a cavity in the core layer of the package substrate, wherein an in-situ electromagnetic shield is formed on the sidewalls of the cavity. In another embodiment, a crystal oscillator is at least partially embedded within the core layer of the package substrate. In another embodiment, a package having a component embedded in the core layer is mounted on a PCB, and a crystal oscillator generating a clock frequency for the package is mounted on the PCB. By embedding components within the core or removing components from the package to be mounted directly on the PCB, the x, y, and z dimensions of a package may be reduced. In addition, in-situ electromagnetic shield may reduce EM noise emitted from the active die.