公开(公告)号：WO2017116763A2

公开(公告)日：2017-07-06

申请号：PCT/US2016/067234

申请日：2016-12-16

Applicant: HEADWAY TECHNOLOGIES, INC. ,  IBM CORPORATION

Inventor： JAN, Guenole ,  WANG, Po-Kang ,  DeBROSSE, John ,  LEE, Yuan-Jen

IPC: G11C29/02 ,  G11C11/16

CPC classification number: G11C11/1673 ,  G11C11/005 ,  G11C11/417 ,  G11C17/02 ,  G11C29/021 ,  G11C29/026 ,  G11C29/028 ,  G11C29/44

Abstract: A circuit and method for adaptive trimming of the reference signal for sensing data during a read operation of magnetic memory cells to improve read margin for the magnetic memory cells. The circuit has a trim one-time programmable memory array programmed with offset trim data applied to magnetic memory array sense amplifiers. Sense amplifier trimming circuits receive and decode the trim data to determine offset trim signal magnitude to adjust the reference signal to improve the read margin. The method sets the offset trim level to each increment of the offset trim level. Data is written and read to the magnetic memory array, the number of errors in the array is accumulated for each setting of the offset trim level. The error levels are compared and the appropriate trim level is programmed to the trim memory cells such that a read margin of the sense amplifier is improved.

Abstract translation: 一种用于在磁存储单元的读取操作期间对参考信号进行自适应修整以用于感测数据的电路和方法，以提高磁存储单元的读取余量。 该电路具有一个微调一次性可编程存储器阵列，该微处理器阵列通过将失调微调数据应用于磁存储器阵列读出放大器而编程。 读出放大器微调电路接收并解码微调数据以确定偏移微调信号幅度以调整参考信号以提高读取裕度。 该方法将偏移修剪水平设置为偏移修剪水平的每个增量。 数据被写入并被读取到磁存储器阵列中，阵列中的错误数量针对偏移微调水平的每个设置而被累积。 比较错误等级，并将适当的修整等级编程到修整存储单元，从而改善读出放大器的读取裕度。

公开(公告)号：WO2017116763A3

公开(公告)日：2017-07-06

申请号：PCT/US2016/067234

申请日：2016-12-16

Applicant: HEADWAY TECHNOLOGIES, INC. ,  IBM CORPORATION

Inventor： JAN, Guenole ,  WANG, Po-Kang ,  DeBROSSE, John ,  LEE, Yuan-Jen

IPC: G11C29/02 ,  G11C11/16 ,  G11C29/44

Abstract: A circuit and method for adaptive trimming of the reference signal for sensing data during a read operation of magnetic memory cells to improve read margin for the magnetic memory cells. The circuit has a trim one-time programmable memory array programmed with offset trim data applied to magnetic memory array sense amplifiers. Sense amplifier trimming circuits receive and decode the trim data to determine offset trim signal magnitude to adjust the reference signal to improve the read margin. The method sets the offset trim level to each increment of the offset trim level. Data is written and read to the magnetic memory array, the number of errors in the array is accumulated for each setting of the offset trim level. The error levels are compared and the appropriate trim level is programmed to the trim memory cells such that a read margin of the sense amplifier is improved.

公开(公告)号：WO2016160578A1

公开(公告)日：2016-10-06

申请号：PCT/US2016/024236

申请日：2016-03-25

Applicant: HEADWAY TECHNOLOGIES, INC.

Inventor： JAN, Guenole ,  WANG, Po-Kang ,  LEE, Yuan-Jen ,  ZHU, Jian ,  LIU, Huanlong

IPC: G11C17/16

CPC classification number: G11C17/18 ,  G11C11/005 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/409 ,  G11C11/419 ,  G11C17/02 ,  G11C17/16 ,  G11C2213/71 ,  H01L27/228 ,  H01L43/12

Abstract: An integrated circuit includes a magnetic OTP memory array formed of multiple magnetic OTP memory cells having an MTJ stack with a fixed magnetic layer, a tunnel barrier insulating layer, a free magnetic layer, and a second electrode. When a voltage is applied across the magnetic OTP memory cell, the resistance of the MTJ stack and the gating transistor form a voltage divider to apply a large voltage across the MTJ stack to breakdown the tunnel barrier to short the fixed layer to the free layer. The integrated circuit has multiple MRAM arrays configured such that each of the multiple MRAM arrays have performance and density criteria that match MOS transistor based memory including SRAM, DRAM, and flash memory. The integrated circuit may include a functional logic unit connected with the magnetic OTP memory arrays and the MRAM arrays for providing digital data storage.

Abstract translation: 集成电路包括由具有固定磁性层的MTJ堆叠的多个磁性OTP存储单元形成的磁性OTP存储器阵列，隧道势垒绝缘层，自由磁性层和第二电极。 当跨越磁性OTP存储单元施加电压时，MTJ堆叠和门控晶体管的电阻形成分压器，以跨越MTJ堆叠施加大电压以击穿隧道势垒以将固定层短路到自由层。 集成电路具有多个MRAM阵列，其配置成使得多个MRAM阵列中的每一个具有与包括SRAM，DRAM和闪速存储器在内的基于MOS晶体管的存储器的性能和密度标准。 集成电路可以包括与磁性OTP存储器阵列连接的功能逻辑单元和用于提供数字数据存储的MRAM阵列。

公开(公告)号：WO2017044447A1

公开(公告)日：2017-03-16

申请号：PCT/US2016/050484

申请日：2016-09-07

Applicant: HEADWAY TECHNOLOGIES, INC.

Inventor： LIU, Huanlong ,  LEE, Yuan-Jen ,  ZHU, Jian ,  JAN, Guenole ,  TONG, Ruth ,  THOMAS, Luc

IPC: H01L43/08 ,  H01L43/10 ,  H01L43/12 ,  H01L43/02

CPC classification number: H01L43/10 ,  G11C11/161 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

Abstract: A magnetic tunnel junction (MTJ) is disclosed wherein a free layer has an interface with a tunnel barrier and a second interface with a metal oxide layer to promote perpendicular magnetic anisotropy (PMA) therein. A diffusion barrier is formed on a side of the metal oxide layer opposite the second interface to prevent non-magnetic metals in a hard mask or electrode from migrating to the second interface and degrading free layer PMA. A second diffusion barrier may be formed between a second electrode and a reference layer. The diffusion barrier may be a single layer of SiN, TiN, TaN, Mo, or CoFeX where X is Zr, P, B, or Ta, or is a multilayer such as CoFeX/Mo wherein CoFeX contacts the metal oxide layer and Mo adjoins a hard mask. As a result, coercivity is maintained or increased in the MTJ after annealing at 400°C for 30 minutes.

Abstract translation: 公开了一种磁性隧道结（MTJ），其中自由层具有与隧道势垒和与金属氧化物层的第二界面的界面，以促进其中的垂直磁各向异性（PMA）。 在金属氧化物层的与第二界面相对的一侧上形成扩散阻挡层，以防止硬掩模或电极中的非磁性金属迁移到第二界面并降解自由层PMA。 可以在第二电极和参考层之间形成第二扩散阻挡层。 扩散阻挡层可以是SiN，TiN，TaN，Mo或CoFeX的单层，其中X是Zr，P，B或Ta，或者是CoFeX / Mo的多层，其中CoFeX与金属氧化物层接触，Mo邻接 一个硬面具 结果，在400℃退火30分钟后，在MTJ中矫顽力得以维持或提高。

公开(公告)号：WO2019074945A1

公开(公告)日：2019-04-18

申请号：PCT/US2018/055043

申请日：2018-10-09

Applicant: HEADWAY TECHNOLOGIES, INC.

Inventor： JAN, Guenole ,  IWATA, Jodi, Mari ,  TONG, Ru-Ying ,  LIU, Huanlong ,  LEE, Yuan-Jen ,  ZHU, Jian

IPC: H01L43/08 ,  H01L43/10 ,  H01L43/12

Abstract: A magnetic tunnel junction (MTJ) is disclosed wherein a free layer (FL) interfaces with a metal oxide (Mox) layer and a tunnel barrier layer to produce interfacial perpendicular magnetic anisotropy (PMA). The Mox layer has a non-stoichiometric oxidation state to minimize parasitic resistance, and comprises a dopant to fill vacant lattice sites thereby blocking oxygen diffusion through the Mox layer to preserve interfacial PMA and high thermal stability at process temperatures up to 400°C. Various methods of forming the doped Mox layer include deposition of the M layer in a reactive environment of O 2 and dopant species in gas form, exposing a metal oxide layer to dopant species in gas form, and ion implanting the dopant. In another embodiment, where the dopant is N, a metal nitride layer is formed on a metal oxide layer, and then an anneal step drives nitrogen into vacant sites in the metal oxide lattice.

公开(公告)号：WO2019099274A1

公开(公告)日：2019-05-23

申请号：PCT/US2018/059803

申请日：2018-11-08

Applicant: HEADWAY TECHNOLOGIES, INC.

Inventor： LEE, Yuan-Jen ,  JAN, Guenole ,  LIU, Huanlong ,  ZHU, Jian

IPC: G11C11/16

Abstract: An initialization process is disclosed for a perpendicular magnetic tunnel junction (p-MTJ) wherein the switching error rate is reduced from a typical range of 30-100 ppm to less than 10 ppm. In one embodiment, an in-plane magnetic field is applied after a final anneal step is performed during memory device fabrication such that all magnetizations in the free layer, and AP1 and AP2 pinned layers are temporarily aligned "in-plane". After the applied field is removed, interfacial perpendicular magnetic anisotropy (PMA) at a tunnel barrier/API interface induces a single AP1 magnetic domain with a magnetization in a first vertical direction. Interfacial PMA at a FL/tunnel barrier interface affords a single FL domain with magnetization in the first direction or opposite thereto. AP2 magnetization is opposite to the first direction as a result of antiferromagnetic coupling with the AP1 layer. Alternatively, a perpendicular- to-plane magnetic field may be applied for initialization.

公开(公告)号：WO2017015294A1

公开(公告)日：2017-01-26

申请号：PCT/US2016/042985

申请日：2016-07-19

Applicant: HEADWAY TECHNOLOGIES, INC.

Inventor： LIU, Huanlong ,  LEE, Yuan-Jen ,  ZHU, Jian ,  JAN, Guenole ,  WANG, Po-Kang

IPC: H01L43/08 ,  H01L43/10 ,  H01L43/12 ,  H01F10/32

CPC classification number: H01L43/10 ,  G11C11/161 ,  H01F10/3272 ,  H01F10/3286 ,  H01F10/329 ,  H01F10/3295 ,  H01F41/307 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

Abstract: A magnetic tunnel junction is disclosed wherein the reference layer and free layer each comprise one layer having a boron content from 25 to 50 atomic%, and an adjoining second layer with a boron content from 1 to 20 atomic%. One of the first and second layers in each of the free layer and reference layer contacts the tunnel barrier. Each boron containing layer has a thickness of 0.1 to 1 nm and may include one or more B layers and one or more Co, Fe, CoFe, or CoFeB layers. As a result, migration of non-magnetic metals along crystalline boundaries to the tunnel barrier is prevented, and the MTJ has a low defect count of around 10 ppm while maintaining an acceptable TMR ratio following annealing to temperatures of about 400°C. The boron containing layers are selected from CoB, FeB, CoFeB and alloys thereof including CoFeNiB.

Abstract translation: 公开了一种磁性隧道结，其中参考层和自由层各自包含具有25至50原子％的硼含量的一个层和具有1至20原子％的硼含量的相邻的第二层。 每个自由层和参考层中的第一层和第二层之一与隧道屏障接触。 每个含硼层的厚度为0.1至1nm，并且可以包括一个或多个B层和一种或多种Co，Fe，CoFe或CoFeB层。 结果，防止非磁性金属沿着结晶边界迁移到隧道势垒，并且MTJ具有约10ppm的低缺陷计数，同时在退火至约400℃的温度之后保持可接受的TMR比。 含硼层选自CoB，FeB，CoFeB及其合金，包括CoFeNiB。

公开(公告)号：WO2018213223A1

公开(公告)日：2018-11-22

申请号：PCT/US2018/032637

申请日：2018-05-15

Applicant: HEADWAY TECHNOLOGIES, INC.

Inventor： ZHU, Jian ,  JAN, Guenole ,  LEE, Yuan-Jen ,  LIU, Huanlong ,  TONG, Ru-Ying ,  IWATA, Jodi, Mari ,  SUNDAR, Vignesh ,  THOMAS, Luc ,  WANG, Yu-Jen ,  PATEL, Sahil

IPC: H01L43/08 ,  H01L43/12

Abstract: A seed layer stack (23t) with a uniform top surface having a peak to peak roughness of 0.5 nm is formed by sputter depositing an amorphous layer (22) on a smoothing layer (21) such as Mg where the latter has a resputtering rate 2 to 30X that of the amorphous layer. The uppermost seed (template) layer (23) is NiW, NiMo, or one or more of NiCr, NiFeCr, and Hf while the bottommost seed layer (20) is one or more of Ta, TaN, Zr, ZrN, Nb, NbN, Mo, MoN, TiN, W, WN, and Ru. Accordingly, perpendicular magnetic anisotropy in an overlying magnetic layer is substantially maintained during high temperature processing up to 400°C and is advantageous for magnetic tunnel junctions in embedded MRAMs, spintronic devices, or in read head sensors. The amorphous seed layer is SiN, TaN, or CoFeM where M is B or another element with a content that makes CoFeM amorphous as deposited.

公开(公告)号：WO2018186971A1

公开(公告)日：2018-10-11

申请号：PCT/US2018/021007

申请日：2018-03-06

Applicant: HEADWAY TECHNOLOGIES, INC

Inventor： LIU, Huanlong ,  LEE, Yuan-Jen ,  ZHU, Jian ,  JAN, Guenole ,  THOMAS, Luc ,  WANG, Po-Kang ,  TONG, Ru-Ying ,  IWATA, Jodi, Mari

IPC: H01L43/08 ,  H01L43/10 ,  H01L43/12

Abstract: A magnetic tunnel junction with perpendicular magnetic anisotropy (PMA MTJ) is disclosed wherein a free layer (14) has an interface (20) with a tunnel barrier (13) and a second interface (21) with an oxide layer (15). A lattice-matching layer (16-1) adjoins an opposite side of the oxide layer with respect to the free layer and is comprised of Co x FeyNi z L w M v or Co x FeyNi z L w wherein L is one of B, Zr, Nb, Hf, Mo, Cu, Cr, Mg, Ta, Ti, Au, Ag, or P, and M is one of Mo, Mg, Ta, Cr, W, or V, (x + y + z + w + v) = 100 atomic%, x + y > 0, and each of v and w are > 0. The lattice-matching layer grows a BCC structure during annealing at about 400°C thereby promoting BCC structure growth in the oxide layer. As a result, free layer PMA is enhanced and maintained to yield improved thermal stability.

公开(公告)号：WO2017091310A1

公开(公告)日：2017-06-01

申请号：PCT/US2016/058449

申请日：2016-10-24

Applicant: HEADWAY TECHNOLOGIES, INC.

Inventor： ZHU, Jian ,  JAN, Guenole ,  LEE, Yuan-Jen ,  LIU, Huanlong ,  TONG, Ru-Ying ,  WANG, Po-Kang

IPC: H01L43/08 ,  H01F10/16 ,  H01F10/32 ,  H01L43/12

CPC classification number: H01L43/08 ,  G11C11/161 ,  H01F10/16 ,  H01F10/30 ,  H01F10/32 ,  H01F10/3254 ,  H01F10/3286 ,  H01L43/02 ,  H01L43/10 ,  H01L43/12

Abstract: A seed layer stack (24) with a smooth top surface having a peak to peak roughness of 0.5 nm is formed by sputter depositing an amorphous layer (22) on a seed layer (21) such as Mg where the seed layer has a resputtering rate 2 to 30X that of the amorphous layer. The uppermost seed layer (23) is a template layer that is NiCr or NiFeCr. As a result, perpendicular magnetic anisotropy in an overlying magnetic layer that is a reference layer, free layer, or dipole layer is substantially maintained during high temperature processing up to 400°C and is advantageous for magnetic tunnel junctions in embedded MRAMs, spintronic devices, or in read head sensors. The amorphous seed layer is SiN, TaN, or CoFeM where M is B or another element with a content that makes CoFeM amorphous as deposited. The seed layer stack may include a bottommost Ta or TaN buffer layer.

Abstract translation: 通过在晶种层（21）上溅射沉积非晶层（22）来形成具有平滑顶面的种子层叠层（24），峰谷粗糙度为0.5nm，所述晶种层（21）例如Mg 其中种子层具有非晶层的2至30倍的再溅射速率。 最上面的种子层（23）是NiCr或NiFeCr的模板层。 结果，在作为参考层，自由层或偶极层的上覆磁层中的垂直磁各向异性在高达400℃的高温处理期间基本上保持不变，并且对于嵌入式MRAM，自旋电子器件等中的磁隧道结是有利的。 或读头传感器。 无定形晶种层是SiN，TaN或CoFeM，其中M是B或另一种元素，其含量使CoFeM在沉积时为非晶态。 种子层堆叠可以包括最下面的Ta或TaN缓冲层。