公开(公告)号：WO2005027192A3

公开(公告)日：2006-12-21

申请号：PCT/US2004028163

申请日：2004-08-30

Applicant: IBM ,  DOKUMACI OMER ,  CHEN HUAJIE ,  CHIDAMBARRAO DURESETI ,  YANG HAINING S

Inventor： DOKUMACI OMER ,  CHEN HUAJIE ,  CHIDAMBARRAO DURESETI ,  YANG HAINING S

IPC: H01L29/73 ,  H01L21/265 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/78

CPC classification number: H01L29/6653 ,  H01L21/26586 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/7833 ,  H01L29/7848

Abstract: A structure and method are provided in which an n-type field effect transistor (NFET) and a p-type field effect transistor (PFET) each have a channel region disposed in a single-crystal layer of a first semiconductor and a stress is applied at a first magnitude to a channel region of the PFET but not at that magnitude to the channel region of the NFET. The stress is applied by a layer of a second semiconductor which is lattice-mismatched to the first semiconductor. The layer of second semiconductor is formed over the source and drain regions and extensions of the PFET at a first distance from the channel region of the PFET and is formed over the source and drain regions of the NFET at a second, greater distance from the channel region of the NFET, or not formed at all in the NFET.

Abstract translation: 提供了一种结构和方法，其中n型场效应晶体管（NFET）和p型场效应晶体管（PFET）各自具有设置在第一半导体的单晶层中的沟道区域并施加应力 在第一幅度上与PFET的沟道区不同，但与NFET的沟道区不同。 应力由第一半导体晶格失配的第二半导体层施加。 第二半导体层形成在PFET的源极和漏极区域以及与PFET的沟道区第一距离处的延伸部分之间，并且形成在NFET的源极和漏极区域之上，距离沟道的第二更远的距离 NFET的区域，或者根本不形成在NFET中。

公开(公告)号：WO2008045989A3

公开(公告)日：2008-09-12

申请号：PCT/US2007081046

申请日：2007-10-11

Applicant: IBM ,  YANG CHIH-CHAO ,  YANG HAINING S ,  WONG KEITH KWONG HON ,  FAROOQ MUKTA G

Inventor： YANG CHIH-CHAO ,  YANG HAINING S ,  WONG KEITH KWONG HON ,  FAROOQ MUKTA G

IPC: H01L21/469

CPC classification number: H01L23/53238 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76883 ,  H01L21/76885 ,  H01L23/53223 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention provides a semiconductor interconnect structure with improved mechanical strength at the interface of the capping layer (61), the underlying dielectric layer (12) and the diffusion barrier (31). The interconnect structure has a portion (41) of the diffusion barrier material (31) embedded in the capping material (61). The barrier (31) can be either partially or fully embedded in the capping layer (61).

Abstract translation: 本发明提供一种半导体互连结构，其在封盖层（61），下面的介电层（12）和扩散阻挡层（31）的界面处具有改进的机械强度。 互连结构具有嵌入封盖材料（61）中的扩散阻挡材料（31）的一部分（41）。 阻挡层（31）可以部分地或完全嵌入封盖层（61）中。

公开(公告)号：WO2007024984A3

公开(公告)日：2008-01-17

申请号：PCT/US2006032974

申请日：2006-08-22

Applicant: IBM ,  YANG HAINING S

Inventor： YANG HAINING S

IPC: H01L29/78 ,  H01L21/8238

CPC classification number: H01L21/823807 ,  H01L21/28052 ,  H01L21/823835 ,  H01L29/4933 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7845 ,  H01L29/7848

Abstract: The present invention relates to a semiconductor device that comprises at least one field effect transistor (FET) containing a source region, a drain region, a channel region, a gate dielectric layer, a gate electrode, and one or more gate sidewall spacers. The gate electrode of such an FET contains an intrinsically stressed gate metal silicide layer, which is laterally confined by one or more gate sidewall spacers and is arranged and constructed for creating stress in the channel region of the FET. Preferably, the semiconductor device comprises at least one p-channel FET, and more preferably, the p-channel FET has a gate electrode with an intrinsically stressed gate metal silicide layer that is laterally confined by one or more gate sidewall spacers and is arranged and constructed for creating compressive stress in the p-channel of the FET.

Abstract translation: 本发明涉及一种半导体器件，其包括至少一个包含源极区域，漏极区域，沟道区域，栅极介电层，栅极电极和一个或多个栅极侧壁间隔物的场效应晶体管（FET）。 这种FET的栅电极包含本征应力的栅极金属硅化物层，其被一个或多个栅极侧壁间隔物侧向限制，并且被布置和构造用于在FET的沟道区域中产生应力。 优选地，半导体器件包括至少一个p沟道FET，并且更优选地，p沟道FET具有栅极电极，其具有被一个或多个栅极侧壁间隔物侧向限制的本征应力栅极金属硅化物层， 构造用于在FET的p沟道中产生压应力。

公开(公告)号：WO2007124472A3

公开(公告)日：2008-07-03

申请号：PCT/US2007067184

申请日：2007-04-23

Applicant: IBM ,  YANG HAINING S

Inventor： YANG HAINING S

IPC: H01L21/311

CPC classification number: H01L21/0337 ,  H01L21/0334 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/76229 ,  H01L21/84 ,  H01L27/0207 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1203 ,  Y10S438/942 ,  Y10S438/947 ,  Y10S977/887

Abstract: A method of processing a substrate of a device comprises the as following steps. Form a cap layer (14) over the substrate (12). Form a dummy layer (DL) over the cap layer (14), the cap layer having a top surface. Etch the dummy layer (DL) forming patterned dummy elements (DA, DB, DC) of variable widths and exposing sidewalls (3ON, 31N, 32N, 33N) of the dummy elements and portions of the top surface of the cap layer (14) aside from the dummy elements. Deposit a spacer layer (18C) over the device covering the patterned dummy elements (DA, DB, DC) and exposed surfaces of the cap layer (14). Etch back the spacer layer (18C) forming sidewall spacers (30N, 31N, 32N, 33N) aside from the sidewalls of the patterned dummy elements (DA, DB, DC) spaced above a minimum spacing and forming super-wide spacers between sidewalls of the patterned dummy elements spaced less than the minimum spacing. Strip the patterned dummy elements. Expose portions of the substrate aside from the sidewall spacers (30N, 31N, 32N, 33N). Pattern exposed portions of the substrate (12) by etching into the substrate.

Abstract translation: 处理装置的基板的方法包括以下步骤。 在衬底（12）上形成覆盖层（14）。 在覆盖层（14）上形成虚设层（DL），覆盖层具有顶表面。 刻蚀虚设层（DL），形成可变宽度的图案化虚设元件（DA，DB，DC）并暴露虚设元件的侧壁（30N，31N，32N，33N）和覆盖层（14）的顶表面的部分; 除了虚拟元素。 在覆盖图案化的虚拟元件（DA，DB，DC）和盖层（14）的暴露表面的器件上沉积间隔层（18C）。 回蚀间隔层（18C），形成侧壁间隔物（30N，31N，32N，33N），除了图案化的虚设元件（DA，DB，DC）的侧壁之外，间隔物的间隔高于最小间隔并且在侧壁之间形成超宽间隔物 图案化的虚设元件间隔小于最小间隔。 剥去图案化的虚设元素。 暴露侧壁间隔物（30N，31N，32N，33N）的部分衬底。 通过蚀刻到衬底中来图案化衬底（12）的部分的图案。

公开(公告)号：WO2006053258A3

公开(公告)日：2008-01-03

申请号：PCT/US2005041051

申请日：2005-11-10

Applicant: IBM ,  YANG HAINING S

Inventor： YANG HAINING S

IPC: H01L21/8238 ,  H01L21/336

CPC classification number: H01L21/823807 ,  H01L21/823835 ,  H01L21/823842 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/7843 ,  H01L29/7845

Abstract: A method of manufacturing complementary metal oxide semiconductor transistors forms different types of transistors such as N-type metal oxide semiconductor (NMOS) transistors and P-type metal oxide semiconductor (PMOS) transistors (first and second type transistors) on a substrate (12). The method forms an optional oxide layer (52) on the NMOS transistors and the PMOS transistors and then covers the NMOS transistors and the PMOS transistors with a hard material (50) such as a silicon nitride layer. Following this, the method patterns portions of the hard material layer (50), such that the hard material layer remains only over the NMOS transistors. Next, the method heats (178, 204) the NMOS transistors and then removes the remaining portions of the hard material layer (50). By creating compressive stress in the gates (22) and tensile stress (70) in the channel regions of the NMOS transistors (NFETs), without creating stress in the gates (20) or channel regions of the PMOS transistors (PFETs), the method improves performance of the NFETs without degrading performance of the PFETs.

Abstract translation: 制造互补金属氧化物半导体晶体管的方法在衬底（12）上形成不同类型的晶体管，例如N型金属氧化物半导体（NMOS）晶体管和P型金属氧化物半导体（PMOS）晶体管（第一和第二类型晶体管） 。 该方法在NMOS晶体管和PMOS晶体管上形成可选的氧化物层（52），然后用诸如氮化硅层的硬质材料（50）覆盖NMOS晶体管和PMOS晶体管。 之后，硬质材料层（50）的方法图形部分，使得硬质材料层仅保留在NMOS晶体管的上方。 接下来，该方法加热（178,204）NMOS晶体管，然后去除硬质材料层（50）的剩余部分。 通过在NMOS晶体管（NFET）的沟道区域中的栅极（22）和拉伸应力（70）中产生压应力，而不在PMOS晶体管（PFET）的栅极（20）或沟道区域中产生应力，该方法 提高NFET的性能，而不降低PFET的性能。

公开(公告)号：WO2005045901A3

公开(公告)日：2006-08-17

申请号：PCT/US2004037049

申请日：2004-11-05

Applicant: IBM ,  STEEGEN AN L ,  YANG HAINING S ,  ZHANG YING

Inventor： STEEGEN AN L ,  YANG HAINING S ,  ZHANG YING

IPC: H01L21/762 ,  H01L21/20 ,  H01L21/265 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/10 ,  H01L29/78

CPC classification number: H01L29/7833 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02532 ,  H01L21/02658 ,  H01L21/26506 ,  H01L21/76224 ,  H01L21/76232 ,  H01L21/76283 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/1054 ,  H01L29/665 ,  H01L29/66575 ,  H01L29/78 ,  H01L29/7842 ,  H01L29/7846 ,  H01L29/7849

Abstract: A method for manufacturing a device including an n-type device and a p-type device. In an aspect of the invention, the method involves doping a portion of a semiconductor substrate (200) and forming a gap (219) in the semiconductor substrate (200) by removing at least a portion of the doped portion of the semiconductor substrate (200). The method further involves growing a strain layer (227) in at least a portion of the gap (219) in the semiconductor substrate (200). For the n-type device, the strain layer (227) is grown on at least a portion which is substantially directly under a channel of the n-type device. For the p-type device, the strain layer is grown on at least a portion which is substantially directly under a source region or drain region of the p-type device and not substantially under a channel of the p-type device.

Abstract translation: 一种制造包括n型器件和p型器件的器件的方法。 在本发明的一个方面，该方法包括通过去除半导体衬底（200）的掺杂部分的至少一部分来掺杂半导体衬底（200）的一部分并在半导体衬底（200）中形成间隙（219） ）。 该方法还包括在半导体衬底（200）中的间隙（219）的至少一部分中生长应变层（227）。 对于n型器件，应变层（227）在基本上直接位于n型器件的沟道下方的至少一部分上生长。 对于p型器件，应变层生长在基本上直接位于p型器件的源极区域或漏极区域的部分上，并且基本上不在p型器件的沟道下生长。

公开(公告)号：WO2006078740A2

公开(公告)日：2006-07-27

申请号：PCT/US2006001768

申请日：2006-01-19

Applicant: IBM ,  CHEN XIANGDONG ,  YANG HAINING S

Inventor： CHEN XIANGDONG ,  YANG HAINING S

IPC: H01L29/78 ,  H01L21/8238

CPC classification number: H01L29/7843 ,  H01L21/823807 ,  H01L21/823842 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure of strained MOSFETs, comprising both PMOSFETs and NMOSFETS, and a method for fabricating strained MOSFETs are disclosed that optimize strain in the MOSFETs, and more particularly maximize the strain in one kind (P or N) of MOSFET and minimize and relax the strain in another kind (N or P) of MOSFET, A strain inducing CA nitride coating having an original full thickness is formed over both the PMOSFETs and the NMOSFETs, wherein the strain inducing coating produces an optimized full strain in one kind of semiconductor device and degrades the performance of the other kind of semiconductor device. The strain inducing CA nitride coating is etched to a reduced thickness over the other kind of semiconductor devices, wherein the reduced thickness of the strain inducing coating relaxes and produces less strain in the other MOSFETs.

Abstract translation: 公开了包括PMOSFET和NMOSFETS的应变MOSFET的半导体结构以及制造应变MOSFET的方法，其优化MOSFET中的应变，并且更特别地使MOSFET的一种（P或N）中的应变最大化并且使 在另一种（N或P）MOSFET的应变中，在PMOSFET和NMOSFET两者上形成具有原始全厚度的A应变诱导氮化镓氮化物涂层，其中应变诱导涂层在一种半导体器件中产生优化的全应变， 降低了另一种半导体器件的性能。 诱导氮化钛涂层的应变被蚀刻到比另一种半导体器件更薄的厚度，其中应变诱导涂层的减小的厚度在其它MOSFET中松弛并产生较小的应变。

公开(公告)号：WO2007127770A3

公开(公告)日：2008-11-13

申请号：PCT/US2007067361

申请日：2007-04-25

Applicant: IBM ,  ONSONGO DAVID M ,  RAUSCH WERNER ,  YANG HAINING S

Inventor： ONSONGO DAVID M ,  RAUSCH WERNER ,  YANG HAINING S

IPC: H01L23/62

CPC classification number: H01L29/7391 ,  H01L29/66356

Abstract: The present invention provides an improved CMOS diode structure with dual gate conductors. Specifically, a substrate comprising a first n-doped region and a second p-doped region is formed. A third region of either n-type or p-type conductivity is located between the first and second regions. A first gate conductor of n-type conductivity and a second gate conductor of p-type conductivity are located over the substrate and adjacent to the first and second regions, respectively. Further, the second gate conductor is spaced apart and isolated from the first gate conductor by a dielectric isolation structure. An accumulation region with an underlying depletion region can be formed in such a diode structure between the third region and the second or the first region, and such an accumulation region preferably has a width that is positively correlated with that of the second or the first gate conductor.

Abstract translation: 本发明提供了具有双栅极导体的改进的CMOS二极管结构。 具体地，形成包括第一n掺杂区域和第二p掺杂区域的衬底。 n型或p型导电性的第三区域位于第一和第二区域之间。 n型导电体的第一栅极导体和p型导电体的第二栅极导体分别位于衬底上并且分别邻近第一和第二区域。 此外，第二栅极导体通过介电隔离结构与第一栅极导体隔开并隔离。 可以在第三区域和第二区域或第一区域之间的这种二极管结构中形成具有底层耗尽区域的积聚区域，并且这样的累积区域优选地具有与第二或第一栅极的宽度正相关的宽度 导体。

公开(公告)号：WO2008094746A3

公开(公告)日：2008-10-09

申请号：PCT/US2008050973

申请日：2008-01-14

Applicant: IBM ,  LI WAI-KIN ,  YANG HAINING S

Inventor： LI WAI-KIN ,  YANG HAINING S

IPC: G03C5/00

CPC classification number: H01L21/31144 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/76816 ,  Y10S438/947 ,  Y10S977/888 ,  Y10S977/895 ,  Y10S977/90

Abstract: The present invention is directed to the formation of sublithographic features in a semi conduct or structure using self-assembling polymers The self-assembling polymers are formed in openings in a hard mask, annealed and then etched, followed by etching of the underlying dielectric material. At least one subiithograpliic feature is formed according to this method. Abo disclosed is an intermediate semiconductor structure in which at least one interconnect wiring feature has a dimension that is defined by a self-assembled block copolymer.

Abstract translation: 本发明涉及使用自组装聚合物在半导体或结构中形成亚光刻特征。将自组装聚合物形成在硬掩模的开口中，退火然后蚀刻，然后蚀刻下面的介电材料。 根据这种方法形成至少一个亚视觉特征。 Abo是一种中间半导体结构，其中至少一个互连布线特征具有由自组装嵌段共聚物限定的尺寸。

公开(公告)号：WO2005045901A8

公开(公告)日：2006-02-02

申请号：PCT/US2004037049

申请日：2004-11-05

Applicant: IBM ,  STEEGEN AN L ,  YANG HAINING S ,  ZHANG YING

Inventor： STEEGEN AN L ,  YANG HAINING S ,  ZHANG YING

IPC: H01L21/20 ,  H01L21/265 ,  H01L21/336 ,  H01L21/762 ,  H01L21/8238 ,  H01L29/10 ,  H01L29/78 ,  H01L

CPC classification number: H01L29/7833 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02532 ,  H01L21/02658 ,  H01L21/26506 ,  H01L21/76224 ,  H01L21/76232 ,  H01L21/76283 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/1054 ,  H01L29/665 ,  H01L29/66575 ,  H01L29/78 ,  H01L29/7842 ,  H01L29/7846 ,  H01L29/7849

Abstract: A method for manufacturing a device including an n-type device and a p-type device. In an aspect of the invention, the method involves doping a portion of a semiconductor substrate and forming a gap in the semiconductor substrate by removing at least a portion of the doped portion of the semiconductor substrate. The method further involves growing a strain layer in at least a portion of the gap in the semiconductor substrate. For the n-type device, the strain layer is grown on at least a portion which is substantially directly under a channel of the n-type device. For the p-type device, the strain layer is grown on at least a portion which is substantially directly under a source region or drain region of the p-type device and not substantially under a channel of the p-type device.

Abstract translation: 一种制造包括n型器件和p型器件的器件的方法。 在本发明的一个方面，该方法包括通过去除半导体衬底的掺杂部分的至少一部分来掺杂半导体衬底的一部分并在半导体衬底中形成间隙。 该方法还包括在半导体衬底中的间隙的至少一部分中生长应变层。 对于n型器件，应变层在基本上直接位于n型器件的沟道下方的至少一部分上生长。 对于p型器件，应变层生长在基本上直接位于p型器件的源极区域或漏极区域的部分上，并且基本上不在p型器件的沟道下生长。