公开(公告)号：WO2014159629A1

公开(公告)日：2014-10-02

申请号：PCT/US2014/024500

申请日：2014-03-12

Applicant: KABUSHIKI KAISHA TOSHIBA ,  SANDISK 3D LLC ,  INTERMOLECULAR, INC.

Inventor： WANG, Yun ,  GOPAL, Vidyut ,  HSUEH, Chien-Lan

IPC: H01L45/00

CPC classification number: H01L45/10 ,  G11C13/0002 ,  G11C13/0007 ,  G11C2213/15 ,  G11C2213/51 ,  G11C2213/56 ,  G11C2213/71 ,  G11C2213/77 ,  H01L45/08 ,  H01L45/1253 ,  H01L45/1266 ,  H01L45/145 ,  H01L45/146 ,  H01L45/1616 ,  H01L45/1625 ,  H01L45/1641

Abstract: Provided are resistive random access memory (ReRAM) cells and methods of fabricating thereof. A stack including a defect source layer, a defect blocking layer, and a defect acceptor layer disposed between the defect source layer and the defect blocking layer may be subjected to annealing. During the annealing, defects are transferred in a controllable manner from the defect source layer to the defect acceptor layer. At the same time, the defects are not transferred into the defect blocking layer thereby creating a lowest concentration zone within the defect acceptor layer. This zone is responsible for resistive switching. The precise control over the size of the zone and the defect concentration within the zone allows substantially improvement of resistive switching characteristics of the ReRAM cell. In some embodiments, the defect source layer includes aluminum oxynitride, the defect blocking layer includes titanium nitride, and the defect acceptor layer includes aluminum oxide.

Abstract translation: 提供了电阻随机存取存储器（ReRAM）单元及其制造方法。 可以对包括缺陷源层，缺陷阻挡层和设置在缺陷源层和缺陷阻挡层之间的缺陷受主层的堆叠进行退火。 在退火过程中，缺陷以可控的方式从缺陷源层转移到缺陷受体层。 同时，缺陷不会转移到缺陷阻挡层中，从而在缺陷受体层内形成最低浓度区。 该区域负责电阻交换。 精确控制区域的尺寸和区域内的缺陷浓度允许ReRAM单元的电阻开关特性得到显着改善。 在一些实施例中，缺陷源层包括氮氧化铝，缺陷阻挡层包括氮化钛，缺陷受主层包括氧化铝。

公开(公告)号：WO2014043630A1

公开(公告)日：2014-03-20

申请号：PCT/US2013/059963

申请日：2013-09-16

Applicant: INTERMOLECULAR, INC

Inventor： HASHIM, Imran ,  CHIANG, Tony ,  GOPAL, Vidyut ,  WANG, Yun

IPC: H01L45/00

CPC classification number: H01L45/1608 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2213/32 ,  G11C2213/51 ,  G11C2213/52 ,  G11C2213/74 ,  G11C2213/79 ,  H01L27/2436 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146

Abstract: Provided are nonvolatile memory assemblies each including a resistive switching layer and current steering element. The steering element may be a transistor connected in series with the switching layer. Resistance control provided by the steering element allows using switching layers requiring low switching voltages and currents. Memory assemblies including such switching layers are easier to embed into integrated circuit chips having other low voltage components, such as logic and digital signal processing components, than, for example, flash memory requiring much higher switching voltages. In some embodiments, provided nonvolatile memory assemblies operate at switching voltages less than about 3.0V and corresponding currents less than 50 microamperes. A memory element may include a metal rich hafnium oxide disposed between a titanium nitride electrode and doped polysilicon electrode. One electrode may be connected to a drain or source of the transistor, while another electrode is connected to a signal line.

Abstract translation: 提供了各自包括电阻式开关层和电流控制元件的非易失性存储器组件。 转向元件可以是与开关层串联连接的晶体管。 由转向元件提供的电阻控制允许使用需要低开关电压和电流的开关层。 包括这种开关层的存储器组件比例如需要高得多的开关电压的闪速存储器更容易嵌入到具有其它低电压组件（例如逻辑和数字信号处理组件）的集成电路芯片中。 在一些实施例中，所提供的非易失性存储器组件在小于约3.0V的开关电压和小于50微安的相应电流下工作。 存储元件可以包括设置在氮化钛电极和掺杂多晶硅电极之间的富含金属的氧化铪。 一个电极可以连接到晶体管的漏极或源极，而另一个电极连接到信号线。

公开(公告)号：WO2013032809A1

公开(公告)日：2013-03-07

申请号：PCT/US2012/051865

申请日：2012-08-22

Applicant: INTERMOLECULAR, INC. ,  WANG, Yun ,  GOPAL, Vidyut ,  HASHIM, Imran ,  PRAMANIK, Dipankar ,  CHIANG, Tony

Inventor： WANG, Yun ,  GOPAL, Vidyut ,  HASHIM, Imran ,  PRAMANIK, Dipankar ,  CHIANG, Tony

IPC: H01L21/20 ,  B82Y40/00

CPC classification number: H01L45/145 ,  C23C16/40 ,  C23C16/45525 ,  H01L21/02175 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02186 ,  H01L21/02189 ,  H01L21/02192 ,  H01L21/02194 ,  H01L21/022 ,  H01L21/0228 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/1266 ,  H01L45/146 ,  H01L45/1608 ,  H01L45/1616

Abstract: Embodiments of the invention generally relate to nonvolatile memory devices, such as a ReRAM cells, and methods for manufacturing such memory devices, which includes optimized, atomic layer deposition (ALD) processes for forming metal oxide film stacks. The metal oxide film stacks contain a metal oxide coupling layer disposed on a metal oxide host layer, each layer having different grain structures/sizes. The interface disposed between the metal oxide layers facilitates oxygen vacancy movement. In many examples, the interface is a misaligned grain interface containing numerous grain boundaries extending parallel to the electrode interfaces, in contrast to the grains in the bulk film extending perpendicular to the electrode interfaces. As a result, oxygen vacancies are trapped and released during switching without significant loss of vacancies. Therefore, the metal oxide film stacks have improved switching performance and reliability during memory cell applications compared to traditional hafnium oxide based stacks of previous memory cells.

Abstract translation: 本发明的实施例一般涉及非易失性存储器件，例如ReRAM单元，以及用于制造这种存储器件的方法，其包括用于形成金属氧化物膜堆叠的优化的原子层沉积（ALD）工艺。 金属氧化物膜堆叠包含设置在金属氧化物主体层上的金属氧化物耦合层，每个层具有不同的晶粒结构/尺寸。 设置在金属氧化物层之间的界面有助于氧空位移动。 在许多示例中，与垂直于电极界面延伸的体膜中的晶粒相反，界面是不对准的晶界，其包含平行于电极界面延伸的许多晶界。 因此，氧空缺在切换期间被捕获和释放，而空位明显损失。 因此，与以前的存储单元的传统的基于氧化铪的堆叠相比，金属氧化物膜堆叠在存储单元应用中具有改进的开关性能和可靠性。

公开(公告)号：WO2013032855A2

公开(公告)日：2013-03-07

申请号：PCT/US2012/052054

申请日：2012-08-23

Applicant: INTERMOLECULAR, INC. ,  TONG, Jinhong ,  HIGUCHI, Randall ,  HASHIM, Imran ,  GOPAL, Vidyut

Inventor： TONG, Jinhong ,  HIGUCHI, Randall ,  HASHIM, Imran ,  GOPAL, Vidyut

IPC: H01L45/00 ,  H01L21/02

CPC classification number: H01L45/1608 ,  H01L45/04 ,  H01L45/146 ,  H01L45/1616 ,  H01L45/1633 ,  H01L45/1658

Abstract: Methods for producing RRAM resistive switching elements having reduced forming voltage include doping to create oxygen deficiencies in the dielectric film. Oxygen deficiencies in a dielectric film promote formation of conductive pathways.

Abstract translation: 制造具有降低的成形电压的RRAM电阻式开关元件的方法包括掺杂以在电介质膜中产生氧缺陷。 电介质膜中的氧缺乏促进导电通路的形成。

公开(公告)号：WO2013119881A1

公开(公告)日：2013-08-15

申请号：PCT/US2013/025237

申请日：2013-02-07

Applicant: INTERMOLECULAR, INC

Inventor： PHAM, Hieu ,  GOPAL, Vidyut ,  HASHIM, Imran ,  MINVIELLE, Tim ,  PRAMANIK, Dipankar

IPC: H01L47/00

CPC classification number: C23C14/345 ,  C23C14/0042 ,  C23C14/0641 ,  C23C14/083 ,  C23C14/225 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/145 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1608 ,  H01L45/1616 ,  H01L45/1625

Abstract: A nonvolatile memory element is disclosed comprising a first electrode, a near-stoichiometric metal oxide memory layer having bistable resistance, and a second electrode in contact with the near-stoichiometric metal oxide memory layer. At least one electrode is a resistive electrode comprising a sub-stoichiometric transition metal nitride or oxynitride, and has a resistivity between 0.1 and 10 Ω cm. The resistive electrode provides the functionality of an embedded current-limiting resistor and also serves as a source and sink of oxygen vacancies for setting and resetting the resistance state of the metal oxide layer. Novel fabrication methods for the second electrode are also disclosed.

Abstract translation: 公开了一种非易失性存储元件，其包括第一电极，具有双稳电阻的近化学计量的金属氧化物存储层，以及与近化学计量的金属氧化物存储层接触的第二电极。 至少一个电极是包括亚化学计量的过渡金属氮化物或氮氧化物的电阻电极，并且具有0.1至10Ωcm的电阻率。 电阻电极提供嵌入式限流电阻器的功能，并且还用作氧空位的源极和吸收器，用于设置和复位金属氧化物层的电阻状态。 还公开了用于第二电极的新颖制造方法。

公开(公告)号：WO2013043561A1

公开(公告)日：2013-03-28

申请号：PCT/US2012/055851

申请日：2012-09-18

Applicant: INTERMOLECULAR, INC. ,  WANG, Yun ,  GOPAL, Vidyut ,  HASHIM, Imran ,  PRAMANIK, Dipankar ,  CHIANG, Tony

Inventor： WANG, Yun ,  GOPAL, Vidyut ,  HASHIM, Imran ,  PRAMANIK, Dipankar ,  CHIANG, Tony

IPC: H01L21/20

CPC classification number: H01L45/146 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1616

Abstract: Embodiments of the invention generally relate to nonvolatile memory devices and methods for manufacturing such memory devices. The methods for forming improved memory devices, such as a ReRAM cells, provide optimized, atomic layer deposition (ALD) processes for forming a metal oxide film stack having a metal oxide buffer layer disposed on or over a metal oxide bulk layer. The metal oxide bulk layer contains a metal-rich oxide material and the metal oxide buffer layer contains a metal-poor oxide material. The metal oxide bulk layer is less electrically resistive than the metal oxide buffer layer since the metal oxide bulk layer is less oxidized or more metallic than the metal oxide buffer layer. In one example, the metal oxide bulk layer contains a metal- rich hafnium oxide material and the metal oxide buffer layer contains a metal-poor zirconium oxide material.

Abstract translation: 本发明的实施例一般涉及用于制造这种存储器件的非易失性存储器件和方法。 用于形成改进的存储器件（例如ReRAM单元）的方法提供优化的原子层沉积（ALD）工艺，用于形成金属氧化物膜堆叠，其具有设置在金属氧化物本体层上或其上的金属氧化物缓冲层。 金属氧化物本体层含有富金属氧化物材料，金属氧化物缓冲层含有贫金属氧化物。 由于金属氧化物本体层比金属氧化物缓冲层氧化较少或更金属，所以金属氧化物本体层的电阻小于金属氧化物缓冲层的电阻。 在一个实例中，金属氧化物本体层含有富含金属的氧化铪材料，金属氧化物缓冲层含有贫金属氧化锆材料。

公开(公告)号：WO2013119882A1

公开(公告)日：2013-08-15

申请号：PCT/US2013/025238

申请日：2013-02-07

Applicant: INTERMOLECULAR, INC.

Inventor： PHAM, Hieu ,  GOPAL, Vidyut ,  HASHIM, Imran ,  WANG, Yun ,  YANG, Hong Sheng

IPC: H01L47/00

CPC classification number: H01L45/08 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/145 ,  H01L45/146 ,  H01L45/147 ,  H01L45/16 ,  H01L45/1616 ,  H01L45/1625 ,  H01L45/1641

Abstract: Embodiments of the invention include nonvolatile memory elements and memory devices comprising the nonvolatile memory elements. Methods for forming the nonvolatile memory elements are also disclosed. The nonvolatile memory element comprises a first electrode layer, a second electrode layer, and a plurality of layers of an oxide disposed between the first and second electrode layers. One of the oxide layers has linear resistance and substoichiometric composition, and the other oxide layer has bistable resistance and near-stoichiometric composition. Preferably, the sum of the two oxide layer thicknesses is between about 20 and about 100, and the oxide layer with bistable resistance has a thickness between about 25% and about 75% of the total thickness. In one embodiment, the oxide layers are formed using reactive sputtering in an atmosphere with controlled flows of argon and oxygen.

Abstract translation: 本发明的实施例包括非易失性存储器元件和包括非易失性存储元件的存储器件。 还公开了形成非易失性存储元件的方法。 非易失性存储元件包括第一电极层，第二电极层和设置在第一和第二电极层之间的多个氧化物层。 氧化物层中的一个具有线性电阻和亚化学计量组成，另一个氧化物层具有双稳态电阻和近化学计量组成。 优选地，两个氧化物层厚度的总和在约20和约100之间，并且具有双稳态电阻的氧化物层具有在总厚度的约25％至约75％之间的厚度。 在一个实施例中，氧化物层在具有受控的氩气和氧气的气氛中使用反应溅射形成。

公开(公告)号：WO2013063617A1

公开(公告)日：2013-05-02

申请号：PCT/US2012/063221

申请日：2012-11-02

Applicant: INTERMOLECULAR, INC. ,  KABUSHIKI KAISHA TOSHIBA ,  SANDISK 3D LLC

Inventor： WANG, Yun ,  CHIANG, Tony, P. ,  GOPAL, Vidyut ,  HASHIM, Imram ,  MINVIELLE, Tim ,  YAMAGUCHI, Takeshi

IPC: H01L21/469

CPC classification number: H01L45/06 ,  H01L45/065 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1641

Abstract: Methods for producing RRAM resistive switching elements having optimal switching behavior include crystalline phase structural changes. Structural changes indicative of optimal switching behavior include hafnium oxide phases in an interfacial region between a resistive switching layer and an electrode.

Abstract translation: 具有最佳切换行为的RRAM电阻式开关元件的制造方法包括晶相结构变化。 指示最佳切换行为的结构变化包括在电阻式开关层和电极之间的界面区域中的氧化铪相。