公开(公告)号：WO2015102899A1

公开(公告)日：2015-07-09

申请号：PCT/US2014/070781

申请日：2014-12-17

Applicant: INTERMOLECULAR, INC.

Inventor： TENDULKAR, Mihir

IPC: H01L21/22

CPC classification number: C23C14/5806 ,  C23C14/0641 ,  C23C14/351 ,  C23C14/352 ,  H01L21/32051 ,  H01L21/76858 ,  H01L27/2409 ,  H01L45/08 ,  H01L45/085 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/16 ,  H01L2924/1435

Abstract: Ternary metal nitride layers suitable for thin-film resistors are fabricated by forming constituent layers of complementary components (e.g., binary nitrides of the different metals, or a binary nitride of one metal and a metallic form of the other metal), then annealing the constituent layers to interdiffuse the materials, thus forming the ternary metal nitride. The constituent layers (e.g., 2-5nm thick) may be sputtered from binary metal nitride targets, from metal targets in a nitrogen-containing ambient, or from metal targets in an inert ambient. Optionally, a nitrogen-containing ambient may also be used for the annealing. The annealing may be 10 seconds to 10 minutes at 500-1000°C and may also process another component on the same substrate (e.g., activate a diode).

Abstract translation: 适用于薄膜电阻器的三元金属氮化物层通过形成互补部件的构成层（例如，不同金属的二元氮化物或一种金属的二元氮化物和另一种金属的金属形式）来制造，然后退火成分 层以相互扩散材料，从而形成三元金属氮化物。 可以从二元金属氮化物靶，来自含氮环境中的金属靶或者在惰性环境中的金属靶溅射构成层（例如2-5nm厚）。 任选地，含氮环境也可用于退火。 退火在500-1000℃可以为10秒至10分钟，并且还可以在同一基板上处理另一组分（例如，激活二极管）。

公开(公告)号：WO2014160439A1

公开(公告)日：2014-10-02

申请号：PCT/US2014/026621

申请日：2014-03-13

Applicant: INTERMOLECULAR, INC.

Inventor： BARABASH, Sergey ,  PRAMANIK, Dipankar

IPC: H01L29/92 ,  H01L21/00 ,  H01L21/20 ,  H01L21/8242

CPC classification number: H01L28/60 ,  H01L21/02156 ,  H01L21/02186 ,  H01L21/02356 ,  H01L21/28088 ,  H01L21/28229 ,  H01L27/1085 ,  H01L2924/0134 ,  H01L2924/0533 ,  H01L2924/05341 ,  H01L2924/10671

Abstract: A dielectric layer can achieve a crystallography orientation similar to a base dielectric layer with a conductive layer disposed between the two dielectric layers. By providing a conductive layer having similar crystal structure and lattice parameters with the base dielectric layer, the crystallography orientation can be carried from the base dielectric layer, across the conductive layer to affect the dielectric layer. The process can be used to form capacitor structure for anisotropic dielectric materials, along the direction of high dielectric constant.

Abstract translation: 电介质层可以实现类似于具有设置在两个电介质层之间的导电层的基极电介质层的结晶取向。 通过提供具有与基底电介质层相似的晶体结构和晶格参数的导电层，晶体取向可以从基底电介质层穿过导电层承载，以影响电介质层。 该方法可以用于形成各向异性介电材料的电容器结构，沿着高介电常数的方向。

公开(公告)号：WO2014159699A1

公开(公告)日：2014-10-02

申请号：PCT/US2014/024820

申请日：2014-03-12

Applicant: INTERMOLECULAR, INC

Inventor： ZHANG, Guizhen ,  CHENG, Jeremy ,  DING, Guowen ,  LE, Minh Huu ,  SCHWEIGERT, Daniel ,  WANG, Yu

IPC: G02B1/10

CPC classification number: C23C14/22 ,  C03C17/36 ,  C03C17/3605 ,  C03C17/3618 ,  C03C17/3644 ,  C03C17/3652 ,  C03C17/366 ,  C03C17/3681 ,  C23C14/0036 ,  C23C14/042 ,  C23C14/14 ,  C23C14/34 ,  G02B1/12 ,  G02B1/14 ,  Y10T428/12542 ,  Y10T428/12549 ,  Y10T428/12611 ,  Y10T428/12778 ,  Y10T428/31678

Abstract: Provided is High Productivity Combinatorial (HPC) testing methodology of semiconductor substrates, each including multiple site isolated regions. The site isolated regions are used for testing different compositions and/or structures of barrier layers disposed over silver reflectors. The tested barrier layers may include all or at least two of nickel, chromium, titanium, and aluminum. In some embodiments, the barrier layers include oxygen. This combination allows using relative thin barrier layers (e.g., 5-30 Angstroms thick) that have high transparency yet provide sufficient protection to the silver reflector. The amount of nickel in a barrier layer may be 5-10% by weight, chromium - 25-30%, titanium and aluminum - 30%-35% each. The barrier layer may be co-sputtered in a reactive or inert environment using one or more targets that include all four metals. An article may include multiple silver reflectors, each having its own barrier layer.

Abstract translation: 提供了半导体衬底的高生产率组合（HPC）测试方法，每个测试方法包括多个现场隔离区域。 位置隔离区域用于测试布置在银反射器上的阻挡层的不同组成和/或结构。 经测试的阻挡层可以包括镍，铬，钛和铝中的全部或至少两种。 在一些实施例中，阻挡层包括氧。 该组合允许使用具有高透明度的相对薄的阻挡层（例如5-30埃厚），同时为银反射器提供足够的保护。 阻挡层中的镍的量可以是5-10重量％，铬25-30％，钛和铝30％-35％。 阻挡层可以在反应性或惰性环境中使用包括所有四种金属的一种或多种目标共溅射。 物品可以包括多个银反射器，每个具有其自己的阻挡层。

公开(公告)号：WO2014159629A1

公开(公告)日：2014-10-02

申请号：PCT/US2014/024500

申请日：2014-03-12

Applicant: KABUSHIKI KAISHA TOSHIBA ,  SANDISK 3D LLC ,  INTERMOLECULAR, INC.

Inventor： WANG, Yun ,  GOPAL, Vidyut ,  HSUEH, Chien-Lan

IPC: H01L45/00

CPC classification number: H01L45/10 ,  G11C13/0002 ,  G11C13/0007 ,  G11C2213/15 ,  G11C2213/51 ,  G11C2213/56 ,  G11C2213/71 ,  G11C2213/77 ,  H01L45/08 ,  H01L45/1253 ,  H01L45/1266 ,  H01L45/145 ,  H01L45/146 ,  H01L45/1616 ,  H01L45/1625 ,  H01L45/1641

Abstract: Provided are resistive random access memory (ReRAM) cells and methods of fabricating thereof. A stack including a defect source layer, a defect blocking layer, and a defect acceptor layer disposed between the defect source layer and the defect blocking layer may be subjected to annealing. During the annealing, defects are transferred in a controllable manner from the defect source layer to the defect acceptor layer. At the same time, the defects are not transferred into the defect blocking layer thereby creating a lowest concentration zone within the defect acceptor layer. This zone is responsible for resistive switching. The precise control over the size of the zone and the defect concentration within the zone allows substantially improvement of resistive switching characteristics of the ReRAM cell. In some embodiments, the defect source layer includes aluminum oxynitride, the defect blocking layer includes titanium nitride, and the defect acceptor layer includes aluminum oxide.

Abstract translation: 提供了电阻随机存取存储器（ReRAM）单元及其制造方法。 可以对包括缺陷源层，缺陷阻挡层和设置在缺陷源层和缺陷阻挡层之间的缺陷受主层的堆叠进行退火。 在退火过程中，缺陷以可控的方式从缺陷源层转移到缺陷受体层。 同时，缺陷不会转移到缺陷阻挡层中，从而在缺陷受体层内形成最低浓度区。 该区域负责电阻交换。 精确控制区域的尺寸和区域内的缺陷浓度允许ReRAM单元的电阻开关特性得到显着改善。 在一些实施例中，缺陷源层包括氮氧化铝，缺陷阻挡层包括氮化钛，缺陷受主层包括氧化铝。

公开(公告)号：WO2014150985A1

公开(公告)日：2014-09-25

申请号：PCT/US2014/024707

申请日：2014-03-12

Applicant: KABUSHIKI KAISHA TOSHIBA ,  SANDISK 3D LLC ,  INTERMOLECULAR, INC.

Inventor： TENDULKAR, Mihir ,  HIGUCHI, Randall ,  HSUEH, Chien-Lan

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/165 ,  H01L27/2409 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1616 ,  H01L45/1625

Abstract: Provided are resistive random access memory (ReRAM) cells and methods of fabricating thereof. A ReRAM cell includes an embedded resistor and resistive switching layer connected in series. The embedded resistor prevents excessive electrical currents through the resistive switching layer, especially when the resistive switching layer is switched into its low resistive state, thereby preventing over-programming. The embedded resistor includes aluminum, nitrogen, and one or more additional metals (other than aluminum). The concentration of each component is controlled to achieve desired resistivity and stability of the embedded resistor. In some embodiments, the resistivity ranges from 0.1 Ohm-centimeter to 40 Ohm- centimeter and remains substantially constant while applying an electrical field of up 8 mega-Volts /centimeter to the embedded resistor. The embedded resistor may be made from an amorphous material, and the material is operable to remain amorphous even when subjected to typical annealing conditions.

Abstract translation: 提供了电阻随机存取存储器（ReRAM）单元及其制造方法。 ReRAM单元包括串联连接的嵌入式电阻和电阻开关层。 嵌入式电阻器阻止通过电阻开关层的过多电流，特别是当电阻式开关层切换到其低电阻状态时，从而防止过度编程。 嵌入式电阻器包括铝，氮和一种或多种另外的金属（除铝以外）。 控制每个组分的浓度以实现嵌入式电阻器的期望的电阻率和稳定性。 在一些实施例中，电阻率范围为0.1欧姆至40欧姆厘米，并且在施加高达8兆伏特/厘米的电场到嵌入式电阻器时保持基本恒定。 嵌入式电阻器可以由非晶材料制成，并且即使经受典型的退火条件，该材料也可操作以保持非晶态。

公开(公告)号：WO2014105792A1

公开(公告)日：2014-07-03

申请号：PCT/US2013/077418

申请日：2013-12-23

Applicant: INTERMOLECULAR, INC ,  GLOBALFOUNDRIES, INC

Inventor： FOSTER, John ,  METZGER, Sven

IPC: H01L21/66

CPC classification number: H01L21/32134 ,  H01L21/28088 ,  H01L21/28123 ,  H01L22/30 ,  H01L29/517 ,  H01L29/6653

Abstract: Provided are methods of High Productivity Combinatorial testing of semiconductor substrates, each including multiple site isolated regions. Each site isolated region includes a titanium nitride structure as well as a hafnium oxide structure and/or a polysilicon structure. Each site isolated region is exposed to an etching solution that includes sulfuric acid, hydrogen peroxide, and hydrogen fluoride. The composition of the etching solution and/or etching conditions are varied among the site isolated regions to study effects of this variation on the etching selectivity of titanium nitride relative to hafnium oxide and/or polysilicon and on the etching rates. The concentration of sulfuric acid and/or hydrogen peroxide in the etching solution may be less than 7 % by volume each, while the concentration of hydrogen fluoride may be between 50 ppm and 200 ppm. In some embodiments, the temperature of the etching solution is maintained at between about 40C and 60C.

Abstract translation: 提供了半导体基板的高效率组合测试方法，每个包括多个位置隔离区域。 每个位置分离区域包括氮化钛结构以及氧化铪结构和/或多晶硅结构。 每个位置分离区域暴露于包括硫酸，过氧化氢和氟化氢的蚀刻溶液。 蚀刻溶液的组成和/或蚀刻条件在位置分离区域之间变化，以研究该变化对氮化钛相对于氧化铪和/或多晶硅的蚀刻选择性的影响以及蚀刻速率。 蚀刻溶液中硫酸和/或过氧化氢的浓度可以小于7体积％，而氟化氢的浓度可以在50ppm和200ppm之间。 在一些实施例中，蚀刻溶液的温度保持在约40℃至60℃之间。

公开(公告)号：WO2014100721A1

公开(公告)日：2014-06-26

申请号：PCT/US2013/077237

申请日：2013-12-20

Applicant: INTERMOLECULAR, INC.

Inventor： LANG, Chi-I ,  NIYOGI, Sandip

IPC: H01L21/31 ,  H01L21/469

CPC classification number: H01L21/02 ,  B01J2219/0043 ,  B01J2219/00443 ,  B01J2219/00635 ,  B01J2219/0075 ,  B01J2219/00756 ,  C23C16/02 ,  C23C16/04 ,  C23C16/45525 ,  H01J37/32422 ,  H01L21/02304 ,  H01L21/02315 ,  H01L21/67207

Abstract: Embodiments provided herein describe methods and systems for processing substrates. A plasma including radical species and charged species is generated. The charged species of the plasma are collected. A substrate is exposed to the radical species of the plasma. A layer is formed on the substrate after exposing the substrate to the radical species.

Abstract translation: 本文提供的实施例描述了用于处理衬底的方法和系统。 产生包括自由基物质和带电物质的等离子体。 收集等离子体的带电物质。 将基底暴露于等离子体的自由基物质。 在将基底暴露于自由基物质之后，在基板上形成层。

公开(公告)号：WO2014043630A1

公开(公告)日：2014-03-20

申请号：PCT/US2013/059963

申请日：2013-09-16

Applicant: INTERMOLECULAR, INC

Inventor： HASHIM, Imran ,  CHIANG, Tony ,  GOPAL, Vidyut ,  WANG, Yun

IPC: H01L45/00

CPC classification number: H01L45/1608 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2213/32 ,  G11C2213/51 ,  G11C2213/52 ,  G11C2213/74 ,  G11C2213/79 ,  H01L27/2436 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146

Abstract: Provided are nonvolatile memory assemblies each including a resistive switching layer and current steering element. The steering element may be a transistor connected in series with the switching layer. Resistance control provided by the steering element allows using switching layers requiring low switching voltages and currents. Memory assemblies including such switching layers are easier to embed into integrated circuit chips having other low voltage components, such as logic and digital signal processing components, than, for example, flash memory requiring much higher switching voltages. In some embodiments, provided nonvolatile memory assemblies operate at switching voltages less than about 3.0V and corresponding currents less than 50 microamperes. A memory element may include a metal rich hafnium oxide disposed between a titanium nitride electrode and doped polysilicon electrode. One electrode may be connected to a drain or source of the transistor, while another electrode is connected to a signal line.

Abstract translation: 提供了各自包括电阻式开关层和电流控制元件的非易失性存储器组件。 转向元件可以是与开关层串联连接的晶体管。 由转向元件提供的电阻控制允许使用需要低开关电压和电流的开关层。 包括这种开关层的存储器组件比例如需要高得多的开关电压的闪速存储器更容易嵌入到具有其它低电压组件（例如逻辑和数字信号处理组件）的集成电路芯片中。 在一些实施例中，所提供的非易失性存储器组件在小于约3.0V的开关电压和小于50微安的相应电流下工作。 存储元件可以包括设置在氮化钛电极和掺杂多晶硅电极之间的富含金属的氧化铪。 一个电极可以连接到晶体管的漏极或源极，而另一个电极连接到信号线。

公开(公告)号：WO2013177557A3

公开(公告)日：2013-11-28

申请号：PCT/US2013/042728

申请日：2013-05-24

Applicant: INTERMOLECULAR, INC

Inventor： TONG, Jinhong

IPC: H01L21/31

Abstract: In some embodiments, the present invention discloses a two-step deposition process for forming hafnium oxide gate dielectric, comprising an interface layer deposition followed by a bulk layer deposition. In the interface layer deposition process, water is used as an oxidizer precursor together with a hafnium-containing precursor. In the bulk layer deposition process, oxygen or ozone is used as an oxidizer precursor together with a hafnium-containing precursor.

公开(公告)号：WO2013123255A1

公开(公告)日：2013-08-22

申请号：PCT/US2013/026219

申请日：2013-02-14

Applicant: INTERMOLECULAR, INC.

Inventor： CHIANG, Tony P.

IPC: H01L25/04 ,  H01L47/00

CPC classification number: H01L45/1608 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/145 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1616

Abstract: Embodiments generally include a method of forming a nonvolatile memory device that contains a resistive switching memory element that has an improved device switching capacity by using multiple layers of variable resistance layers. In one embodiment, the resistive switching element comprises at least three layers of variable resistance materials to increase the number of logic states. Each variable resistance layer may have an associated high resistance state and an associated low resistance state. As the resistance of each variable resistance layer determines the digital data bit that is stored, the multiple variable resistance layers per memory element allows for additional data storage without the need to further increase the density of nonvolatile memory devices. Typically, resistive switching memory elements may be formed as part of a high-capacity nonvolatile memory integrated circuit, which can be used in various electronic devices, such as digital cameras, mobile telephones, handheld computers, and music players.

Abstract translation: 实施例通常包括形成非易失性存储器件的方法，该非易失性存储器件包含通过使用多层可变电阻层而具有改进的器件开关容量的电阻式开关存储器元件。 在一个实施例中，电阻式开关元件包括至少三层可变电阻材料，以增加逻辑状态的数量。 每个可变电阻层可以具有相关联的高电阻状态和相关联的低电阻状态。 由于每个可变电阻层的电阻决定了存储的数字数据位，每个存储元件的多个可变电阻层允许额外的数据存储，而不需要进一步增加非易失性存储器件的密度。 通常，电阻式开关存储器元件可以形成为可用于各种电子设备（例如数码相机，移动电话，手持式计算机和音乐播放器）的大容量非易失性存储器集成电路的一部分。