公开(公告)号：WO2014100183A3

公开(公告)日：2014-06-26

申请号：PCT/US2013/076134

申请日：2013-12-18

Applicant: INVENSAS CORPORATION

Inventor： HABA, Belgacem ,  AYATOLLAHI, Fatima, Lina ,  NEWMAN, Michael ,  MONADGEMI, Pezhman

IPC: H01L21/768 ,  H01L23/48

Abstract: Microelectronic elements and methods of their manufacture are disclosed. A microelectronic element (100) may include a substrate including an opening (108) extending through a semiconductor region (102) of the substrate, a dielectric layer (114) covering a wall (110) of the opening within at least a first portion of the opening, a first metal (118) disposed within the first portion of the opening, a second metal disposed within a second portion of the opening. The second metal may form at least part of a contact of the microelectronic element.

公开(公告)号：WO2014189881A1

公开(公告)日：2014-11-27

申请号：PCT/US2014/038711

申请日：2014-05-20

Applicant: INVENSAS CORPORATION

Inventor： WOYCHIK, Charles ,  UZOH, Cyprian Emeka ,  NEWMAN, Michael ,  CASKEY, Terrence ,  MONADGEMI, Pezhman

IPC: H01L21/768

CPC classification number: H01L21/76877 ,  H01L21/32055 ,  H01L21/76802 ,  H01L21/76841 ,  H01L21/76858 ,  H01L21/76873 ,  H01L21/76874 ,  H01L21/76898 ,  H01L23/147 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49866 ,  H01L23/525 ,  H01L23/53233 ,  H01L23/53238 ,  H01L2224/16 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Structures and methods of forming the same are disclosed herein. In one embodiment, a structure comprises a region (102) having first and second oppositely facing surfaces (104, 106). A barrier region (110) overlies the region. An alloy region (112) overlies the barrier region. The alloy region includes a first metal and one or more elements selected from the group consisting of silicon (Si), germanium (Ge), indium (Id), boron (B), arsenic (As), antimony (Sb), tellurium (Te), or cadmium (Cd).

Abstract translation: 本文公开了其形成的结构和方法。 在一个实施例中，结构包括具有第一和第二相对面的表面（104,106）的区域（102）。 屏障区域（110）覆盖该区域。 合金区域（112）覆盖在阻挡区域上。 合金区域包括第一金属和一种或多种选自硅（Si），锗（Ge），铟（Id），硼（B），砷（As），锑（Sb），碲（ Te）或镉（Cd）。

公开(公告)号：WO2014130959A1

公开(公告)日：2014-08-28

申请号：PCT/US2014/018057

申请日：2014-02-24

Applicant: INVENSAS CORPORATION

Inventor： NEWMAN, Michael ,  UZOH, Cyprian Emeka ,  MONADGEMI, Pezhman ,  CASKEY, Terrence

IPC: H01L23/14 ,  H01L23/498 ,  H01L21/48

CPC classification number: H01L21/486 ,  H01L23/147 ,  H01L23/49827 ,  H01L2224/13 ,  H01L2224/16225 ,  H05K1/111 ,  H05K3/0014 ,  H05K3/4038 ,  Y10T29/49117

Abstract: An interposer can have conductive elements at a first side and terminals at a second side opposite therefrom, for connecting with a microelectronic element and a second component, respectively. The component can include a first element having a thermal expansion coefficient less than 10 ppm/°C, and an insulating second element, with a plurality of openings extending from the second side through the second element towards the first element. Conductive structure extending through the openings in the second element and through the first element electrically connects the terminals with the conductive elements.

Abstract translation: 插入件可以在第一侧具有导电元件，并且在与其相对的第二侧具有端子，用于分别与微电子元件和第二元件连接。 该组件可以包括具有小于10ppm /℃的热膨胀系数的第一元件和绝缘的第二元件，其中多个开口从第二侧延伸穿过第二元件朝向第一元件。 延伸穿过第二元件中的开口并通过第一元件的导电结构将端子与导电元件电连接。

公开(公告)号：WO2014100200A1

公开(公告)日：2014-06-26

申请号：PCT/US2013/076158

申请日：2013-12-18

Applicant: INVENSAS CORPORATION

Inventor： UZOH, Cyprian Emeka ,  MONADGEMI, Pezhman ,  CASKEY, Terrence ,  AYATOLLAHI, Fatima Lina ,  HABA, Belgacem ,  WOYCHIK, Charles G. ,  NEWMAN, Michael

IPC: H01L23/48 ,  H01L23/367

CPC classification number: H01L23/49827 ,  H01L21/76829 ,  H01L21/76898 ,  H01L23/36 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/3736 ,  H01L23/481 ,  H01L23/49838 ,  H01L23/49866 ,  H01L2924/00 ,  H01L2924/0002

Abstract: A method for making an interconnect element includes depositing a thermally conductive layer (38) on an in-process unit (10). The in-process unit includes a semiconductor material layer (12) defining a surface and edges surrounding the surface, a plurality of conductive elements (20), each conductive element having a first portion extending through the semiconductor material layer and a second portion extending from the surface of the semiconductor material layer. Dielectric coatings (28) extend over at least the second portion of each conductive element. The thermally conductive layer (38) is deposited on the in-process unit at a thickness of at least 10 microns so as to overlie a portion of the surface of the semiconductor material layer between the second portions of the conductive elements with the dielectric coatings positioned between the conductive elements and the thermally conductive layer.

Abstract translation: 制造互连元件的方法包括在工艺处理单元（10）上沉积导热层（38）。 处理单元包括限定表面和围绕表面的边缘的半导体材料层（12），多个导电元件（20），每个导电元件具有延伸穿过半导体材料层的第一部分和从第二部分延伸的第二部分 半导体材料层的表面。 电介质涂层（28）至少在每个导电元件的第二部分上延伸。 导热层（38）以至少10微米的厚度沉积在处理单元上，以覆盖导电元件的第二部分之间的半导体材料层的表面的一部分，其中定位的电介质涂层 在导电元件和导热层之间。

公开(公告)号：WO2015084660A1

公开(公告)日：2015-06-11

申请号：PCT/US2014/067496

申请日：2014-11-25

Applicant: INVENSAS CORPORATION

Inventor： CAO, Andrew ,  NEWMAN, Michael

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/16 ,  H01L23/522

CPC classification number: H01L21/4853 ,  H01L21/486 ,  H01L23/13 ,  H01L23/147 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/562 ,  H01L24/02 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/48 ,  H01L25/0657 ,  H01L25/16 ,  H01L2224/0231 ,  H01L2224/0237 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05569 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73257 ,  H01L2224/81424 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81464 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2224/45099 ,  H01L2924/00012

Abstract: A component, e.g., interposer has first and second opposite sides, conductive elements at the first side and terminals at the second side. The terminals can connect with another component, for example. A first element at the first side can comprise a first material having a thermal expansion coefficient less than 10 ppm/°C, and a second element at the second side can comprise a plurality of insulated structures separated from one another by at least one gap. Conductive structure extends through at least one insulated structure and is electrically coupled with the terminals and the conductive elements. The at least one gap can reduce mechanical stress in connections between the terminals and another component.

Abstract translation: 诸如插入件的部件具有第一和第二相对侧，第一侧的导电元件和第二侧的端子。 终端可以连接另一个组件，例如。 第一侧的第一元件可以包括具有小于10ppm /℃的热膨胀系数的第一材料，第二侧的第二元件可以包括通过至少一个间隙彼此分开的多个绝缘结构。 导电结构延伸穿过至少一个绝缘结构，并与端子和导电元件电耦合。 所述至少一个间隙可以减小端子与另一部件之间的连接中的机械应力。

公开(公告)号：WO2014022780A1

公开(公告)日：2014-02-06

申请号：PCT/US2013/053437

申请日：2013-08-02

Applicant: INVENSAS CORPORATION

Inventor： CASKEY, Terrence ,  MOHAMMED, Ilyas ,  UZOH, Cyprian, Emeka ,  WOYCHIK, Charles ,  NEWMAN, Michael ,  MONADGEMI, Pezhman ,  CO, Reynaldo ,  CHAU, Ellis ,  HABA, Belgacem

IPC: H01L23/48 ,  H01L23/12

CPC classification number: H01L25/105 ,  H01L21/486 ,  H01L23/3114 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0655 ,  H01L2224/02379 ,  H01L2224/04042 ,  H01L2224/16225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45664 ,  H01L2224/48091 ,  H01L2224/48108 ,  H01L2224/48227 ,  H01L2224/73207 ,  H01L2224/73257 ,  H01L2225/1023 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/381 ,  H05K1/0298 ,  H05K3/46 ,  Y10T29/49126 ,  Y10T29/49162 ,  H01L2924/00012 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: A method for making an interposer includes forming a plurality of wire bonds bonded to one or more first surfaces of a first element. A dielectric encapsulation is formed contacting an edge surface of the wire bonds which separates adjacent wire bonds from one another. Further processing comprises removing at least portions of the first element, wherein the interposer has first and second opposite sides separated from one another by at least the encapsulation, and the interposer having first contacts and second contacts at the first and second opposite sides, respectively, for electrical connection with first and second components, respectively, the first contacts being electrically connected with the second contacts through the wire bonds.

Abstract translation: 制造插入件的方法包括形成结合到第一元件的一个或多个第一表面的多个引线键合。 形成电介质封装，其接触将引线接合部彼此分隔开的引线接合的边缘表面。 进一步的处理包括去除第一元件的至少一部分，其中插入件具有通过至少封装相互隔开的第一和第二相对侧，并且插入件分别在第一和第二相对侧具有第一接触和第二接触， 分别与第一和第二部件电连接，第一触点通过引线键与第二触点电连接。

公开(公告)号：WO2014204771A1

公开(公告)日：2014-12-24

申请号：PCT/US2014/042064

申请日：2014-06-12

Applicant: INVENSAS CORPORATION

Inventor： HABA, Belgacem ,  WOYCHIK, Charles, G. ,  UZOH, Cyprian, Emeka ,  NEWMAN, Michael ,  CASKEY, Terrence

IPC: H01L21/60 ,  H01L23/485 ,  H01L21/98 ,  H01L25/065

CPC classification number: H01L24/13 ,  H01L21/563 ,  H01L23/564 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/02372 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0347 ,  H01L2224/03912 ,  H01L2224/03914 ,  H01L2224/0401 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05557 ,  H01L2224/05568 ,  H01L2224/05571 ,  H01L2224/05609 ,  H01L2224/05611 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/05664 ,  H01L2224/10145 ,  H01L2224/1146 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/11903 ,  H01L2224/13024 ,  H01L2224/13025 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13157 ,  H01L2224/13164 ,  H01L2224/1319 ,  H01L2224/14517 ,  H01L2224/1601 ,  H01L2224/16057 ,  H01L2224/16058 ,  H01L2224/16104 ,  H01L2224/16105 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16503 ,  H01L2224/17505 ,  H01L2224/17517 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81001 ,  H01L2224/81007 ,  H01L2224/811 ,  H01L2224/81139 ,  H01L2224/8192 ,  H01L2224/83104 ,  H01L2224/9201 ,  H01L2224/9212 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2924/00014 ,  H05K1/181 ,  H05K3/30 ,  Y10T29/4913 ,  H01L2924/00012 ,  H01L2924/01015 ,  H01L2924/01074 ,  H01L2224/05552

Abstract: Microelectronic assemblies and methods for making the same are disclosed herein. In one embodiment, a method of forming a microelectronic assembly comprises: assembling first and second components (102, 128) to have first major surfaces (104, 130) of the first and second components (102, 128) facing one another and spaced apart from one another by a predetermined spacing, the first component (102) having first and second oppositely-facing major surfaces (104, 106), a first thickness extending in a first direction between the first and second major surfaces (104, 106), and a plurality of first metal connection elements (112) at the first major surface (104), the second component (128) having a plurality of second metal connection elements (132) at the first major surface (130) of the second component (128); and then plating (electroplating or electroless plating) a plurality of metal connector regions (146) each connecting and extending continuously between a respective first connection element (112) and a corresponding second connection element (132) opposite the respective first connection element (112) in the first direction. The first and second metal connection elements (112, 132) may comprise metal vias (116, 134) in the components (102, 128) or metal pads (118) at the surface of the components (102, 128), the metal vias (116, 134) or the metal pads (118) being covered by plated metal regions (114). A first seed layer (126) may be formed overlying the major surface of the first component (102) before the plating process, wherein uncovered portions of the first seed layer (126) are removed after plating the metal connector regions (146). Similarly, a second seed layer (144) may be formed overlying the major surface of the second component (128). A plurality of barrier regions (152) may overlie the sidewalls of at least one of the metal connector regions (146), the first plated metal regions (114) or the second plated metal regions. At least some corresponding first and second metal connection elements (112, 132) may optionally not share a common axis. At least some first and second surfaces (113, 131) of the first metal connection elements (112) and the respective second metal connection elements (132) connected thereto may optionally not be parallel to a common plane.

Abstract translation: 本文公开了微电子组件及其制造方法。 在一个实施例中，形成微电子组件的方法包括：组装第一和第二部件（102,128）以使第一和第二部件（102,128）彼此面对并间隔开的第一主表面（104,130） 第一部件（102）具有第一和第二相对的主表面（104,106），在第一和第二主表面（104,106）之间沿第一方向延伸的第一厚度， 以及在所述第一主表面（104）处的多个第一金属连接元件（112），所述第二部件（128）在所述第二部件的所述第一主表面（130）处具有多个第二金属连接元件（132） 128）; 然后电镀（电镀或化学镀）多个金属连接器区域（146），每个金属连接器区域在相应的第一连接元件（112）和与相应的第一连接元件（112）相对的对应的第二连接元件（132）之间连续延伸并延伸， 在第一个方向。 第一和第二金属连接元件（112,132）可以包括组件（102,128）中的金属通孔（116,134）或元件（102,128）的表面处的金属焊盘（118），金属通孔 （116,134）或金属焊盘（118）被电镀金属区域（114）覆盖。 可以在电镀工艺之前，在第一部件（102）的主表面上形成第一种子层（126），其中在镀覆金属连接器区域（146）之后，去除第一籽晶层（126）的未覆盖部分。 类似地，可以形成第二种子层（144），覆盖第二部件（128）的主表面。 多个阻挡区域（152）可以覆盖金属连接器区域（146），第一电镀金属区域（114）或第二电镀金属区域中的至少一个的侧壁。 至少一些对应的第一和第二金属连接元件（112,132）可以可选地不共享公共轴线。 第一金属连接元件（112）和连接到其上的相应的第二金属连接元件（132）的至少一些第一和第二表面（113,131）可以可选地不平行于公共平面。

公开(公告)号：WO2014152756A1

公开(公告)日：2014-09-25

申请号：PCT/US2014/027699

申请日：2014-03-14

Applicant: INVENSAS CORPORATION

Inventor： WOYCHIK, Charles ,  UZOH, Cyprian, Emeka ,  NEWMAN, Michael ,  CASKEY, Terrence

IPC: H01L23/31 ,  H01L23/48 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L27/14634 ,  H01L21/4846 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/56 ,  H01L21/561 ,  H01L21/563 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5384 ,  H01L24/11 ,  H01L24/16 ,  H01L24/17 ,  H01L24/80 ,  H01L24/81 ,  H01L24/97 ,  H01L27/14618 ,  H01L27/14636 ,  H01L27/1469 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68377 ,  H01L2221/68381 ,  H01L2224/13 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81191 ,  H01L2224/81801 ,  H01L2224/97 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/351 ,  H05K1/0298 ,  H01L2224/81 ,  H01L2924/00

Abstract: A microelectronic assembly including a dielectric region, a plurality of electrically conductive elements, an encapsulant, and a microelectronic element are provided. The encapsulant may have a coefficient of thermal expansion (CTE) no greater than twice a CTE associated with at least one of the dielectric region or the microelectronic element.

Abstract translation: 提供了包括电介质区域，多个导电元件，密封剂和微电子元件的微电子组件。 密封剂可以具有不大于与电介质区域或微电子元件中的至少一个相关联的CTE的两倍的热膨胀系数（CTE）。

公开(公告)号：WO2014100186A2

公开(公告)日：2014-06-26

申请号：PCT/US2013/076137

申请日：2013-12-18

Applicant: INVENSAS CORPORATION

Inventor： UZOH, Cyprian, Emeka ,  MONADGEMI, Pezhman ,  NEWMAN, Michael ,  WOYCHIK, Charles, G. ,  CASKEY, Terrence

IPC: H01L21/768

CPC classification number: H01L21/76898 ,  H01L21/31053 ,  H01L21/561 ,  H01L21/6835 ,  H01L21/768 ,  H01L21/76841 ,  H01L21/76877 ,  H01L21/78 ,  H01L23/481 ,  H01L24/94 ,  H01L2221/68327 ,  H01L2221/68381 ,  H01L2924/0002 ,  H01L2924/12042 ,  H01L2924/00

Abstract: Methods of forming a microelectronic assembly and the resulting structures and devices are disclosed herein. In one embodiment, a method of forming a microelectronic assembly includes removing material exposed at portions of a surface of a substrate to form a processed substrate having a plurality of thinned portions separated by integral supporting portions of the processed substrate having a thickness greater than a thickness of the thinned portions, at least some of the thinned portions including a plurality of electrically conductive interconnects extending in a direction of the thicknesses of the thinned portions and exposed at the surface; and removing the supporting portions of the substrate to sever the substrate into a plurality of individual thinned portions, at least some individual thinned portions including the interconnects.

Abstract translation: 本文公开了形成微电子组件以及所得到的结构和器件的方法。 在一个实施例中，一种形成微电子组件的方法包括：去除在衬底的表面的一部分处暴露的材料，以形成经处理的衬底，该衬底具有由经处理的衬底的整体支撑部分分隔的多个减薄部分，该整体支撑部分的厚度大于厚度 所述变薄部分中的至少一些包括多个导电互连，所述导电互连在所述变薄部分的厚度的方向上延伸并且在所述表面处暴露; 以及移除衬底的支撑部分以将衬底切割成多个单独的薄化部分，至少一些单独的薄化部分包括互连。