公开(公告)号：WO2017027090A1

公开(公告)日：2017-02-16

申请号：PCT/US2016/036326

申请日：2016-06-08

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： LU, Zhenyu ,  ALSMEIER, Johann ,  MAO, Daxin ,  SHI, Stephen ,  KOKA, Sateesh ,  MAKALA, Raghuveer S. ,  MATAMIS, George ,  LEE, Yao-sheng ,  GE, Chun

IPC: H01L27/115

CPC classification number: H01L27/1157 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11575 ,  H01L27/11582

Abstract: A monolithic three-dimensional memory device includes a first memory block containing a plurality of memory sub-blocks located on a substrate. Each memory sub-block includes a set of memory stack structures and a portion of alternating layers laterally surrounding the set of memory stack structures. The alternating layers include insulating layers and electrically conductive layers. A first portion of a neighboring pair of memory sub-blocks is laterally spaced from each other along a first horizontal direction by a backside contact via structure. A subset of the alternating layers contiguously extends between a second portion of the neighboring pair of memory sub-blocks through a gap in a bridge region between two portions of the backside contact via structure that are laterally spaced apart along a second horizontal direction to provide a connecting portion between the neighboring pair of memory sub-blocks.

Abstract translation: 单片三维存储器件包括包含位于衬底上的多个存储子块的第一存储块。 每个存储器子块包括一组存储器堆叠结构和交替层的一部分横向围绕该组存储器堆叠结构。 交替层包括绝缘层和导电层。 相邻的一对存储器子块的第一部分通过背面接触通孔结构沿着第一水平方向彼此横向间隔开。 交替层的子集在相邻的一对存储子块的第二部分之间通过沿着第二水平方向横向间隔开的背侧接触通孔结构的两个部分之间的桥接区域中的间隙连续地延伸，以提供 在相邻的一对存储器子块之间的连接部分。

公开(公告)号：WO2017019177A1

公开(公告)日：2017-02-02

申请号：PCT/US2016/036086

申请日：2016-06-06

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： KANAKAMEDALA, Senaka ,  MAKALA, Raghuveer S. ,  ZHANG, Yanli ,  LEE, Yao-Sheng ,  MATAMIS, George

IPC: H01L29/788 ,  H01L29/792 ,  H01L27/115

CPC classification number: H01L27/11578 ,  H01L21/28282 ,  H01L27/0207 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/4234 ,  H01L29/42344 ,  H01L29/66833 ,  H01L29/7926

Abstract: An alternating stack of insulating layers and sacrificial material layers is formed on a substrate. Separator insulator structures can be optionally formed through the alternating stack. Memory opening are formed through the alternating stack, and the sacrificial material layers are removed selective to the insulating layers. Electrically conductive layers are formed in the lateral recesses by deposition of at least one conductive material. Metal-semiconductor alloy regions are appended to the electrically conductive layers by depositing at least a semiconductor material and inducing reaction of the semiconductor material with the material of the electrically conductive layers and/or a sacrificial metal layer. Memory stack structures can be formed in the memory openings and directly on the metal-semiconductor alloy regions of the electrically conductive layers.

Abstract translation: 在衬底上形成交替堆叠的绝缘层和牺牲材料层。 分离器绝缘体结构可以可选地通过交替堆叠形成。 通过交替堆叠形成存储器开口，并且牺牲材料层被选择性地去除绝缘层。 通过沉积至少一种导电材料，在侧向凹槽中形成导电层。 通过至少沉积半导体材料并引起半导体材料与导电层和/或牺牲金属层的材料的反应，将金属 - 半导体合金区附加到导电层。 存储器堆叠结构可以形成在存储器开口中，并且直接在导电层的金属 - 半导体合金区域上形成。

公开(公告)号：WO2016167984A1

公开(公告)日：2016-10-20

申请号：PCT/US2016/025394

申请日：2016-03-31

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： SHARANGPANI, Rahul ,  MAKALA, Raghuveer S. ,  KOKA, Sateesh ,  KUBO, Tomohiro ,  ARIYOSHI, Junichi ,  MATAMIS, George

IPC: H01L27/115

CPC classification number: H01L27/1157 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582

Abstract: Resistance of a semiconductor channel in three-dimensional memory stack structures can be reduced by forming a metal-semiconductor alloy region between a vertical semiconductor channel and a horizontal semiconductor channel located within a substrate. The metal-semiconductor alloy region can be formed by recessing a portion of the semiconductor material layer in the semiconductor substrate underneath a memory opening after formation of a memory film, selectively depositing a metallic material in the recess region, depositing a vertical semiconductor channel, and reacting the deposited metallic material with an adjacent portion of the semiconductor material layer and the vertical semiconductor channel. A sacrificial dielectric material layer can be formed on the memory film prior to the selective deposition of the metallic material. The vertical semiconductor channel can be formed in a single deposition process, thereby eliminating any interface therein and minimizing the resistance of the vertical semiconductor channel.

Abstract translation: 通过在位于衬底内的垂直半导体沟道和水平半导体沟道之间形成金属 - 半导体合金区域，可以减少三维存储堆叠结构中的半导体沟道的电阻。 金属 - 半导体合金区域可以通过在形成记忆膜之后在存储器开口下面的半导体衬底中的一部分半导体材料层凹陷来形成，在凹陷区域中选择性地沉积金属材料，沉积垂直半导体沟道，以及 使沉积的金属材料与半导体材料层和垂直半导体沟道的相邻部分反应。 在金属材料的选择性沉积之前，可以在记忆膜上形成牺牲介电材料层。 可以在单个沉积工艺中形成垂直半导体沟道，从而消除其中的任何界面并使垂直半导体沟道的电阻最小化。

公开(公告)号：WO2017034646A1

公开(公告)日：2017-03-02

申请号：PCT/US2016/036656

申请日：2016-06-09

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： LU, Zhenyu ,  MAO, Daxin ,  MIYATA, Koji ,  ARIYOSHI, Junichi ,  ALSMEIER, Johann ,  MATAMIS, George ,  SHI, Wenguang ,  XU, Jiyin ,  HU, Xiaolong ,  LIN, Andrew ,  YU, Jixin

IPC: H01L27/115

CPC classification number: H01L27/11582 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02636 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11575

Abstract: A method of fabricating a memory device is provided. The method includes forming a first alternating stack of insulator layers and spacer material layers over a semiconductor substrate, etching the first alternating stack to expose a single crystalline semiconductor material, forming a first epitaxial semiconductor pedestal on the single crystalline semiconductor material, such that the first epitaxial semiconductor pedestal is in epitaxial alignment with the single crystalline semiconductor material, forming an array of memory stack structures through the first alternating stack, and forming at least one semiconductor device over the first epitaxial semiconductor pedestal.

Abstract translation: 提供一种制造存储器件的方法。 该方法包括在半导体衬底上形成绝缘体层和隔离材料层的第一交替叠层，蚀刻第一交替堆叠以暴露单晶半导体材料，在单晶半导体材料上形成第一外延半导体基座，使得第一 外延半导体基座与单晶半导体材料进行外延对准，通过第一交替叠层形成存储堆栈结构的阵列，并在第一外延半导体基座上形成至少一个半导体器件。

公开(公告)号：WO2016099628A1

公开(公告)日：2016-06-23

申请号：PCT/US2015/053841

申请日：2015-10-02

Applicant: SANDISK TECHNOLOGIES, LLC

Inventor： MAKALA, Raghuveer S. ,  SHARANGPANI, Rahul ,  KANAKAMEDALA, Senaka Krishna ,  LIANG, Xiaofeng ,  MATAMIS, George ,  KOKA, Sateesh ,  ALSMEIER, Johann

IPC: H01L27/115

CPC classification number: H01L27/11582 ,  G11C16/0483 ,  G11C16/06 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/42364 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/7883

Abstract: A plurality of blocking dielectric portions can be formed between a memory stack structure and an alternating stack of first material layers and second material layers by selective deposition of a dielectric material layer. The plurality of blocking dielectric portions can be formed after removal of the second material layers selective to the first material layers by depositing a dielectric material on surfaces of the memory stack structure while avoiding deposition on surfaces of the first material layers. A deposition inhibitor material layer or a deposition promoter material layer can be optionally employed. Alternatively, the plurality of blocking dielectric portions can be formed on surfaces of the second material layers while avoiding deposition on surfaces of the first material layers after formation of the memory opening and prior to formation of the memory stack structure. The plurality of blocking dielectric portions are vertically spaced annular structures.

Abstract translation: 通过选择性沉积介电材料层，可以在存储器堆叠结构和第一材料层和第二材料层的交替堆叠之间形成多个阻挡电介质部分。 通过在存储堆叠结构的表面上沉积电介质材料，同时避免沉积在第一材料层的表面上，可以在去除对第一材料层选择性的第二材料层之后形成多个阻挡电介质部分。 可以任选地使用沉积抑制剂材料层或沉积促进剂材料层。 或者，可以在形成存储器开口之后并且在形成存储器堆叠结构之前，在第二材料层的表面上形成多个阻挡电介质部分，同时避免在第一材料层的表面上沉积。 多个阻挡电介质部分是垂直间隔开的环形结构。