公开(公告)号：WO2016099628A1

公开(公告)日：2016-06-23

申请号：PCT/US2015/053841

申请日：2015-10-02

Applicant: SANDISK TECHNOLOGIES, LLC

Inventor： MAKALA, Raghuveer S. ,  SHARANGPANI, Rahul ,  KANAKAMEDALA, Senaka Krishna ,  LIANG, Xiaofeng ,  MATAMIS, George ,  KOKA, Sateesh ,  ALSMEIER, Johann

IPC: H01L27/115

CPC classification number: H01L27/11582 ,  G11C16/0483 ,  G11C16/06 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/42364 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/7883

Abstract: A plurality of blocking dielectric portions can be formed between a memory stack structure and an alternating stack of first material layers and second material layers by selective deposition of a dielectric material layer. The plurality of blocking dielectric portions can be formed after removal of the second material layers selective to the first material layers by depositing a dielectric material on surfaces of the memory stack structure while avoiding deposition on surfaces of the first material layers. A deposition inhibitor material layer or a deposition promoter material layer can be optionally employed. Alternatively, the plurality of blocking dielectric portions can be formed on surfaces of the second material layers while avoiding deposition on surfaces of the first material layers after formation of the memory opening and prior to formation of the memory stack structure. The plurality of blocking dielectric portions are vertically spaced annular structures.

Abstract translation: 通过选择性沉积介电材料层，可以在存储器堆叠结构和第一材料层和第二材料层的交替堆叠之间形成多个阻挡电介质部分。 通过在存储堆叠结构的表面上沉积电介质材料，同时避免沉积在第一材料层的表面上，可以在去除对第一材料层选择性的第二材料层之后形成多个阻挡电介质部分。 可以任选地使用沉积抑制剂材料层或沉积促进剂材料层。 或者，可以在形成存储器开口之后并且在形成存储器堆叠结构之前，在第二材料层的表面上形成多个阻挡电介质部分，同时避免在第一材料层的表面上沉积。 多个阻挡电介质部分是垂直间隔开的环形结构。

公开(公告)号：WO2017052698A1

公开(公告)日：2017-03-30

申请号：PCT/US2016/036578

申请日：2016-06-09

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： PERI, Somesh ,  MAKALA, Raghuveer S. ,  KOKA, Sateesh ,  SHARANGPANI, Rahul

IPC: H01L27/115

CPC classification number: H01L27/115 ,  H01L21/283 ,  H01L27/0207 ,  H01L27/1157 ,  H01L27/11582

Abstract: An alternating stack of insulating layers and sacrificial material layers can be formed over a substrate. Memory stack structures and a backside trench are formed through the alternating stack. Backside recesses are formed by removing the sacrificial material layers from the backside trench selective to the insulating layers. A cobalt-containing material is deposited such that the cobalt-containing material continuously extends at least between a neighboring pair of cobalt-containing material portions in respective backside recesses. An anneal is performed at an elevated temperature to migrate vertically-extending portions of the cobalt-containing material into the backside recesses, thereby forming vertically separated cobalt-containing material portions confined within the backside recesses. Sidewalls of the insulating layers may be rounded or tapered to facilitate migration of the cobalt-containing material.

Abstract translation: 绝缘层和牺牲材料层的交替堆叠可以形成在衬底上。 通过交替堆叠形成存储器堆叠结构和背面沟槽。 通过从对绝缘层选择性的背面沟槽去除牺牲材料层而形成背面凹部。 沉积含钴材料，使得含钴材料至少在相应的背面凹槽中的相邻的一对含钴材料部分之间连续延伸。 在升高的温度下进行退火以将含钴材料的垂直延伸部分迁移到背面凹槽中，从而形成限制在背面凹槽内的垂直分离的含钴材料部分。 绝缘层的侧壁可以是圆形或锥形以促进含钴材料的迁移。

公开(公告)号：WO2017027090A1

公开(公告)日：2017-02-16

申请号：PCT/US2016/036326

申请日：2016-06-08

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： LU, Zhenyu ,  ALSMEIER, Johann ,  MAO, Daxin ,  SHI, Stephen ,  KOKA, Sateesh ,  MAKALA, Raghuveer S. ,  MATAMIS, George ,  LEE, Yao-sheng ,  GE, Chun

IPC: H01L27/115

CPC classification number: H01L27/1157 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11575 ,  H01L27/11582

Abstract: A monolithic three-dimensional memory device includes a first memory block containing a plurality of memory sub-blocks located on a substrate. Each memory sub-block includes a set of memory stack structures and a portion of alternating layers laterally surrounding the set of memory stack structures. The alternating layers include insulating layers and electrically conductive layers. A first portion of a neighboring pair of memory sub-blocks is laterally spaced from each other along a first horizontal direction by a backside contact via structure. A subset of the alternating layers contiguously extends between a second portion of the neighboring pair of memory sub-blocks through a gap in a bridge region between two portions of the backside contact via structure that are laterally spaced apart along a second horizontal direction to provide a connecting portion between the neighboring pair of memory sub-blocks.

Abstract translation: 单片三维存储器件包括包含位于衬底上的多个存储子块的第一存储块。 每个存储器子块包括一组存储器堆叠结构和交替层的一部分横向围绕该组存储器堆叠结构。 交替层包括绝缘层和导电层。 相邻的一对存储器子块的第一部分通过背面接触通孔结构沿着第一水平方向彼此横向间隔开。 交替层的子集在相邻的一对存储子块的第二部分之间通过沿着第二水平方向横向间隔开的背侧接触通孔结构的两个部分之间的桥接区域中的间隙连续地延伸，以提供 在相邻的一对存储器子块之间的连接部分。

公开(公告)号：WO2017052697A1

公开(公告)日：2017-03-30

申请号：PCT/US2016/036349

申请日：2016-06-08

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： PERI, Somesh ,  KOKA, Sateesh ,  MAKALA, Raghuveer S.

IPC: H01L27/115

CPC classification number: H01L27/115 ,  H01L27/0207 ,  H01L27/11551 ,  H01L27/1157 ,  H01L27/11578 ,  H01L27/11582

Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory stack structures and a backside trench are formed through the alternating stack. Backside recesses are formed by removing the sacrificial material layers through the backside trench selective to the insulating layers. A cobalt portion is formed in each backside recess. A cobalt-semiconductor alloy portion can be formed on each cobalt portion by depositing a semiconductor material layer on the cobalt portions and reacting the semiconductor material with surface regions of the cobalt portions. A residual portion of the cobalt-semiconductor alloy formed above the alternating stack can be removed by an anisotropic etch or by a planarization process. A combination of a cobalt portion and a cobalt-semiconductor alloy portion within each backside recess can be employed as a word line of a three-dimensional memory device.

Abstract translation: 绝缘层和牺牲材料层的交替堆叠形成在衬底上。 通过交替堆叠形成存储器堆叠结构和背面沟槽。 通过对绝缘层选择性的背面沟槽去除牺牲材料层而形成背面凹部。 在每个后侧凹槽中形成钴部分。 通过在钴部分上沉积半导体材料层并使半导体材料与钴部分的表面区域反应，可以在每个钴部分上形成钴 - 半导体合金部分。 可以通过各向异性蚀刻或通过平坦化处理来去除在交替堆叠之上形成的钴 - 半导体合金的残留部分。 作为三维存储装置的字线，可以采用各背面凹部内的钴部和钴半导体合金部的组合。

公开(公告)号：WO2016167984A1

公开(公告)日：2016-10-20

申请号：PCT/US2016/025394

申请日：2016-03-31

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： SHARANGPANI, Rahul ,  MAKALA, Raghuveer S. ,  KOKA, Sateesh ,  KUBO, Tomohiro ,  ARIYOSHI, Junichi ,  MATAMIS, George

IPC: H01L27/115

CPC classification number: H01L27/1157 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582

Abstract: Resistance of a semiconductor channel in three-dimensional memory stack structures can be reduced by forming a metal-semiconductor alloy region between a vertical semiconductor channel and a horizontal semiconductor channel located within a substrate. The metal-semiconductor alloy region can be formed by recessing a portion of the semiconductor material layer in the semiconductor substrate underneath a memory opening after formation of a memory film, selectively depositing a metallic material in the recess region, depositing a vertical semiconductor channel, and reacting the deposited metallic material with an adjacent portion of the semiconductor material layer and the vertical semiconductor channel. A sacrificial dielectric material layer can be formed on the memory film prior to the selective deposition of the metallic material. The vertical semiconductor channel can be formed in a single deposition process, thereby eliminating any interface therein and minimizing the resistance of the vertical semiconductor channel.

Abstract translation: 通过在位于衬底内的垂直半导体沟道和水平半导体沟道之间形成金属 - 半导体合金区域，可以减少三维存储堆叠结构中的半导体沟道的电阻。 金属 - 半导体合金区域可以通过在形成记忆膜之后在存储器开口下面的半导体衬底中的一部分半导体材料层凹陷来形成，在凹陷区域中选择性地沉积金属材料，沉积垂直半导体沟道，以及 使沉积的金属材料与半导体材料层和垂直半导体沟道的相邻部分反应。 在金属材料的选择性沉积之前，可以在记忆膜上形成牺牲介电材料层。 可以在单个沉积工艺中形成垂直半导体沟道，从而消除其中的任何界面并使垂直半导体沟道的电阻最小化。

公开(公告)号：WO2016209379A1

公开(公告)日：2016-12-29

申请号：PCT/US2016/031331

申请日：2016-05-06

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： SHARANGPANI, Rahul ,  KOKA, Sateesh ,  MAKALA, Raghuveer S. ,  RANGANATHAN, Srikanth ,  JUANITAS, Mark ,  ALSMEIER, Johann

IPC: H01L21/28 ,  H01L27/115

CPC classification number: H01L27/11582 ,  H01L21/02178 ,  H01L21/0228 ,  H01L21/02299 ,  H01L21/02321 ,  H01L21/02356 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/31116 ,  H01L21/31122 ,  H01L21/31155 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L29/7883

Abstract: A method of manufacturing a semiconductor structure includes forming a stack of alternating layers comprising insulating layers and spacer material layers over a semiconductor substrate, forming a memory opening through the stack, forming an aluminum oxide layer having a horizontal portion at a bottom of the memory opening and a vertical portion at least over a sidewall of the memory opening, where the horizontal portion differs from the vertical portion by at least one of structure or composition, and selectively etching the horizontal portion selective to the vertical portion.

Abstract translation: 一种制造半导体结构的方法包括在半导体衬底上形成包括绝缘层和隔离材料层的交替层叠，形成通过堆叠的存储器开口，形成在存储器开口底部具有水平部分的氧化铝层 以及至少在存储器开口的侧壁上的垂直部分，其中水平部分与竖直部分不同于结构或组成中的至少一个，并且选择性地蚀刻对垂直部分有选择性的水平部分。