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    THREE-DIMENSIONAL MEMORY DEVICE HAVING STRESSED VERTICAL SEMICONDUCTOR CHANNELS AND METHOD OF MAKING THE SAME
    5.
    发明申请
    THREE-DIMENSIONAL MEMORY DEVICE HAVING STRESSED VERTICAL SEMICONDUCTOR CHANNELS AND METHOD OF MAKING THE SAME 审中-公开

    公开(公告)号：WO2020131170A1

    公开(公告)日：2020-06-25

    申请号：PCT/US2019/048170

    申请日：2019-08-26

    Applicant: SANDISK TECHNOLOGIES LLC

    Inventor： SHARANGPANI, Rahul ,  MAKALA, Raghuveer S. ,  RAJASHEKHAR, Adarsh ,  ZHOU, Fei ,  RANGANATHAN, Srikanth ,  NISHIDA, Akio ,  IIZUKA, Toshihiro

    IPC: H01L27/11529 ,  H01L27/11556 ,  H01L21/02

    Abstract: Three-dimensional memory devices include structures that induce a vertical tensile stress in vertical semiconductor channels to enhance charge carrier mobility. Vertical tensile stress may be induced by a laterally compressive stress applied by stressor pillar structure. The stressor pillar structures can include a stressor material such as a dielectric metal oxide material, silicon nitride, thermal silicon oxide or a semiconductor material having a greater lattice constant than that of the channel. Vertical tensile stress may be induced by a compressive stress applied by electrically conductive layers that laterally surround the vertical semiconductor channel, or by a stress memorization technique that captures a compressive stress from sacrificial material layers. Vertical tensile stress can be generated by a source-level pinning layer that prevents vertical expansion of the vertical semiconductor channel. Vertical tensile stress can be induced by using a layer stack including polysilicon and a silicon-germanium alloy for the vertical semiconductor channel.

    THREE-DIMENSIONAL PHASE CHANGE MEMORY ARRAY INCLUDING DISCRETE MIDDLE ELECTRODES AND METHODS OF MAKING THE SAME
    6.
    发明申请
    THREE-DIMENSIONAL PHASE CHANGE MEMORY ARRAY INCLUDING DISCRETE MIDDLE ELECTRODES AND METHODS OF MAKING THE SAME 审中-公开

    公开(公告)号：WO2019236162A1

    公开(公告)日：2019-12-12

    申请号：PCT/US2019/019879

    申请日：2019-02-27

    Applicant: SANDISK TECHNOLOGIES LLC

    Inventor： ZHOU, Fei ,  MAKALA, Raghuveer S. ,  PETTI, Christopher J. ,  SHARANGPANI, Rahul ,  RAJASHEKHAR, Adarsh ,  YANG, Seung-Yeul

    IPC: H01L45/00

    Abstract: Alternating stacks of insulating strips and sacrificial material strips are formed over a substrate. A laterally alternating sequence of pillar cavities and pillar structures can be formed within each of the line trenches. A phase change memory cell including a discrete metal portion, a phase change memory material portion, and a selector material portion is formed at each level of the sacrificial material strips at a periphery of each of the pillar cavities. Vertical bit lines are formed in the two-dimensional array of pillar cavities. Remaining portions of the sacrificial material strips are replaced with electrically conductive word line strips. Pathways for providing an isotropic etchant for the sacrificial material strips and a reactant for a conductive material of the electrically conductive word line strips may be provided by a backside trench, or by removing the pillar structures to provide backside openings.

    THREE-DIMENSIONAL MEMORY DEVICE WITH ANNULAR BLOCKING DIELECTRICS AND METHOD OF MAKING THEREOF
    9.
    发明申请
    THREE-DIMENSIONAL MEMORY DEVICE WITH ANNULAR BLOCKING DIELECTRICS AND METHOD OF MAKING THEREOF 审中-公开

    公开(公告)号：WO2019089152A1

    公开(公告)日：2019-05-09

    申请号：PCT/US2018/051987

    申请日：2018-09-20

    Applicant: SANDISK TECHNOLOGIES LLC

    Inventor： ZHOU, Fei ,  MAKALA, Raghuveer S. ,  SHARANGPANI, Rahul ,  RAJASHEKHAR, Adarsh

    IPC: H01L27/11556 ,  H01L27/11524 ,  H01L21/768 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11529 ,  H01L27/11573

    Abstract: A memory opening is formed through an alternating stack of insulating layers and sacrificial material layers located over a substrate. Annular recesses are formed around the memory opening by laterally recessing the sacrificial material layers with respect to the insulating layers. Annular metal portions are formed over recessed sidewalls of the sacrificial material layers within each of the annular recesses by a selective deposition process. Annular backside blocking dielectrics are formed selectively on inner sidewalls of the annular metal portions employing a layer of a self-assembly material that covers surfaces of the insulating layers and inhibits deposition of a dielectric material thereupon. A memory stack structure is formed in the memory opening, and the sacrificial material layers are replaced with electrically conductive layers. The annular backside blocking dielectrics provide electrical isolation for the annular metal portions, which function as control gate electrodes.

    THREE-DIMENSIONAL MEMORY DEVICE INCLUDING VERTICALLY OFFSET DRAIN SELECT LEVEL LAYERS AND METHOD OF MAKING THEREOF
    10.
    发明申请
    THREE-DIMENSIONAL MEMORY DEVICE INCLUDING VERTICALLY OFFSET DRAIN SELECT LEVEL LAYERS AND METHOD OF MAKING THEREOF 审中-公开

    公开(公告)号：WO2018236427A1

    公开(公告)日：2018-12-27

    申请号：PCT/US2018/019885

    申请日：2018-02-27

    Applicant: SANDISK TECHNOLOGIES LLC

    Inventor： ZHOU, Fei ,  SHARANGPANI, Rahul ,  ZHANG, Yanli ,  MAKALA, Raghuveer S. ,  KANAKAMEDALA, Senaka Krishna

    IPC: H01L27/1157 ,  H01L27/11582

    Abstract: A three-dimensional memory device can be formed by first forming an alternating stack of insulating layers and stack level spacer material layers over a substrate. The stack level spacer material layers can be formed as, or are subsequently replaced with, stack level electrically conductive layers. A bottommost insulating spacer layer is formed with recesses that form grooves that are laterally spaced apart. Drain select level electrically conductive layers are formed over protruding portions and within the grooves of the bottommost insulating spacer layer by anisotropic deposition and isotropic etch back of a conductive material. Additional insulating spacer layers may be formed by anisotropic deposition of an insulating material. Additional drain select level electrically conductive layers can be formed by anisotropic deposition and isotropic etch back of additional conductive material. Memory stack structures can be formed through the drain select level electrically conductive layers and through the alternating stack.

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