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    MULTI-DIE INTEGRATED CIRCUIT STRUCTURE WITH UNDERFILL
    1.
    发明申请
    MULTI-DIE INTEGRATED CIRCUIT STRUCTURE WITH UNDERFILL 审中-公开
    多层集成电路结构不完整

    公开(公告)号：WO2012074619A1

    公开(公告)日：2012-06-07

    申请号：PCT/US2011/057138

    申请日：2011-10-20

    Applicant: XILINX, INC.

    Inventor： RAHMAN, Arifur

    IPC: H01L21/56 ,  H01L25/065

    CPC classification number: H01L21/563 ,  H01L23/544 ,  H01L25/0655 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54473 ,  H01L2224/73203

    Abstract: In one embodiment, a method of forming a multi-die semiconductor device is provided. A plurality of dice (402 and 404) is mounted on a semiconductor substrate (426), and neighboring ones of the dice are separated by a distance (420) at which a first one of the neighboring dice (404) will contact a meniscus (406) of a flange (416) of the neighboring die during underfill to form a capillary bridge between the neighboring dice (402 and 404). Solder bumps are reflowed to electrically connect contact terminals of the plurality of dice to contact terminals on a top surface of the substrate (512). Underfill is deposited along one or more edges of one or more of the plurality of dice (516). As a result of the capillary bridge formed between neighboring dice, flow of underfill is induced between the bottom surfaces of the neighboring dice and the top surface of the substrate. The dispensed underfill is cured (518).

    Abstract translation: 在一个实施例中，提供了一种形成多芯片半导体器件的方法。 多个骰子（402和404）安装在半导体衬底（426）上，并且相邻的骰子被分开距离（420），在该距离处，相邻骰子（404）中的第一个将接触弯月面（420） 406）在底部填充期间相邻模具的凸缘（416）形成在相邻骰子（402和404）之间的毛细管桥。 焊接凸块被回流以将多个裸片的接触端子电连接到衬底（512）的顶表面上的接触端子。 底部填充物沿着多个骰子（516）中的一个或多个的一个或多个边缘沉积。 作为在相邻骰子之间形成的毛细管桥的结果，在相邻骰子的底表面和衬底的顶表面之间引起底部填充物的流动。 分配的底部填充物被固化（518）。

    THROUGH SILICON VIA WITH IMPROVED RELIABILITY
    2.
    发明申请
    THROUGH SILICON VIA WITH IMPROVED RELIABILITY 审中-公开
    通过硅可以改善可靠性

    公开(公告)号：WO2012064435A1

    公开(公告)日：2012-05-18

    申请号：PCT/US2011/055129

    申请日：2011-10-06

    Applicant: XILINX, INC.

    Inventor： RAHMAN, Arifur ,  BANIJAMALI, Bahareh

    IPC: H01L21/768 ,  H01L23/48 ,  H01L23/498

    CPC classification number: H01L21/76898 ,  H01L21/486 ,  H01L23/147 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2224/0401

    Abstract: A semiconductor device includes a substrate (105) having a top surface (109) and a bottom surface (1 10), and a through-silicon via (TSV) (103) extending from the top surface (109) of the substrate (105) to the bottom surface (1 10) of the substrate (105), the TSV (103) having a height and a side profile extending along a longitudinal axis (200), where the side profile has an upper segment (201, 21 1, 301, 401, 501, 601 ) forming a first angle relative to the longitudinal axis (200), and a lower segment (202, 212, 302, 402, 502, 603) forming a second angle relative to the longitudinal axis (200), where the second angle is different than the first angle, and where the lower segment (202, 212, 302, 402, 502, 603) has a height that is less than 20% of the height of the TSV (103).

    Abstract translation: 半导体器件包括具有顶表面（109）和底表面（110）的衬底（105）和从衬底（105）的顶表面（109）延伸的穿硅通孔（TSV）（103） ）到衬底（105）的底表面（110），TSV（103）具有沿着纵向轴线（200）延伸的高度和侧面轮廓，其中侧部轮廓具有上部段（201,21 ，相对于纵向轴线（200）形成第一角度的相对于纵向轴线（200）形成第二角度的下部段（202,212,302,402,502,603），301,301,501,601， ），其中第二角度不同于第一角度，并且其中下部段（202,212,302,402,502,603）具有小于TSV（103）的高度的20％的高度。

    SEMICONDUCTOR STACK ASSEMBLY HAVING REDUCED THERMAL SPREADING RESISTANCE AND METHODS OF MAKING SAME
    3.
    发明申请
    SEMICONDUCTOR STACK ASSEMBLY HAVING REDUCED THERMAL SPREADING RESISTANCE AND METHODS OF MAKING SAME 审中-公开
    具有降低的热膨胀电阻的半导体堆叠组件及其制造方法

    公开(公告)号：WO2009111186A1

    公开(公告)日：2009-09-11

    申请号：PCT/US2009/034721

    申请日：2009-02-20

    Applicant: XILINX, INC.

    Inventor： RAHMAN, Arifur

    IPC: H01L25/065 ,  H01L23/433 ,  H01L25/16

    CPC classification number: H01L25/0652 ,  H01L23/3128 ,  H01L25/16 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06568 ,  H01L2225/06589 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19104

    Abstract: Semiconductor assemblies having reduced thermal spreading resistance and methods of making the same are described. In an example, a semiconductor device (101) includes a primary integrated circuit (IC) die (102) and at least one secondary IC die (104) mounted on the primary IC die (102). A heat extraction element (110) includes a base (109) mounted to the semiconductor device (101) such that each of the at least one secondary IC die (104) is between the primary IC die (102) and the heat extraction element (110). At least one dummy fill (106) is adjacent the at least one secondary IC die (104), and each thermally couples the primary IC die (102) to the heat extraction element (110).

    Abstract translation: 描述了具有降低的热扩散电阻的半导体组件及其制造方法。 在一个示例中，半导体器件（101）包括主集成电路（IC）管芯（102）和安装在主IC管芯（102）上的至少一个次级IC管芯（104）。 散热元件（110）包括安装到半导体器件（101）的基座（109），使得至少一个次级IC芯片（104）中的每一个位于主IC管芯（102）和热提取元件 110）。 至少一个虚拟填充物（106）与所述至少一个次级IC管芯（104）相邻，并且各自将所述主IC管芯（102）热耦合到所述热提取元件（110）。

    STRESS-AWARE DESIGN FOR INTEGRATED CIRCUITS
    6.
    发明申请
    STRESS-AWARE DESIGN FOR INTEGRATED CIRCUITS 审中-公开
    集成电路应力设计

    公开(公告)号：WO2012173683A1

    公开(公告)日：2012-12-20

    申请号：PCT/US2012/031299

    申请日：2012-03-29

    Applicant: XILINX, INC. ,  RAHMAN, Arifur

    Inventor： RAHMAN, Arifur

    IPC: H01L25/065 ,  H01L23/14 ,  H01L23/48 ,  H01L23/498 ,  H01L23/00

    CPC classification number: H01L25/0652 ,  H01L23/147 ,  H01L23/49827 ,  H01L23/562 ,  H01L25/0657 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2224/0401

    Abstract: A method of circuit design involving an integrated circuit (IC) having an interposer can include identifying an active resource implemented within the IC (200, 500) within a zone (465, 470, 535) of the interposer (205, 505) exposed to an amount of stress that exceeds a normalized amount of stress on the interposer and selectively assigning an element of the circuit design to be implemented within the IC to the active resource according to a stress-aware analysis of the circuit design as implemented within the IC. Another zone (620) is characterized by a substantially normalized stress throughout the other zone.

    Abstract translation: 涉及具有插入器的集成电路（IC）的电路设计的方法可以包括识别在所述IC（200,500）内实现的活动资源，所述活动资源在所述插入器（205,505）暴露于 一定量的应力超过内插器上的归一化应力量，并且根据在IC内实现的电路设计的应力感知分析，选择性地将要在IC内实现的电路设计的元件分配给有源资源。 另一个区域（620）的特征在于在整个另一个区域内基本归一化的应力。

    APPARATUS AND METHOD FOR TESTING OF STACKED DIE STRUCTURE
    8.
    发明申请
    APPARATUS AND METHOD FOR TESTING OF STACKED DIE STRUCTURE 审中-公开
    用于测试堆叠式结构的装置和方法

    公开(公告)号：WO2011008309A1

    公开(公告)日：2011-01-20

    申请号：PCT/US2010/024682

    申请日：2010-02-19

    Applicant: XILINX, INC.

    Inventor： RAHMAN, Arifur ,  PAN, Hong-tsz ,  NGUYEN, Bang-Thu

    IPC: G01R31/3185

    CPC classification number: G01R31/318544 ,  H01L2224/16145

    Abstract: An integrated circuit device includes a stacked die (102) and a base die (101) having probe pads (306, 111 -116) that directly couple to test logic (305, 104) of the base die to implement a scan chain for testing of the integrated circuit device. The base die further includes contacts (107) disposed on a back side of the base die and through-die vias (310, 121 -128) coupled to the contacts and coupled to programmable logic (550, 314, 105) of the base die. The base die also includes a first probe pad (111) configured to couple test input, a second probe pad (112) configured to couple test output, and a third probe pad (113) configured to couple control signals. Test logic (305) of the base die is configured to couple to additional test logic (405) of the stacked die to implement the scan chain. The probe pads (306, 111 -116) are coupled directly to the test logic (305, 104) such that configuration of the programmable logic (550, 314, 105) is not required to implement the scan chain.

    Abstract translation: 集成电路装置包括堆叠管芯（102）和具有直接连接到基座管芯的测试逻辑（305,104）的探针焊盘（306,111-116）的基底管芯（101），以实现用于测试的扫描链 的集成电路器件。 基模还包括设置在基模的背侧的触点（107）和耦合到触点的通孔（310,121-128），并连接到基模的可编程逻辑（550,314,105） 。 基模还包括配置成耦合测试输入的第一探针焊盘（111），被配置为耦合测试输出的第二探针焊盘（112）和被配置为耦合控制信号的第三探针焊盘（113）。 基模的测试逻辑（305）被配置为耦合到堆叠管芯的附加测试逻辑（405）以实现扫描链。 探针焊盘（306,111-116）直接耦合到测试逻辑（305,104），使得不需要可编程逻辑（550,314,105）的配置来实现扫描链。

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