公开(公告)号：WO2015120196A1

公开(公告)日：2015-08-13

申请号：PCT/US2015/014685

申请日：2015-02-05

Applicant: XILINX, INC.

Inventor： WU, Paul, Y. ,  NIAZI, Sarajuddin ,  ANDERSON, Raymond, E. ,  RAMALINGAM, Suresh

IPC: H01L23/538

CPC classification number: H01R12/71 ,  H01L23/49816 ,  H01L23/5385 ,  H01L23/5386 ,  H01L2224/16 ,  H01L2924/0002 ,  H01R43/0235 ,  Y10T29/49117 ,  H01L2924/00

Abstract: An apparatus for placement between a package and an integrated circuit board is provided. The apparatus may include: an insert (112). The insert may have: a substrate having a top side and a bottom side; a first set of pads (114) at the top side of the substrate; a second set of pads (114) at the bottom side of the substrate; and a plurality of vias (116) in the substrate, the vias (116) connecting respective pads (114) in the first set to respective pads (114) in the second set; wherein the insert (112) has a thickness that is less than a spacing between the package and the integrated circuit board.

Abstract translation: 提供一种用于放置在封装和集成电路板之间的装置。 该装置可以包括：插入件（112）。 插入件可以具有：具有顶侧和底侧的基板; 在衬底的顶侧的第一组焊盘（114）; 在衬底的底侧的第二组衬垫（114）; 和多个通孔（116），所述通孔（116）将第一组中的相应衬垫（114）连接到第二组中的相应衬垫（114）; 其中插入件（112）的厚度小于封装和集成电路板之间的间隔。

公开(公告)号：WO2013158151A1

公开(公告)日：2013-10-24

申请号：PCT/US2012/067082

申请日：2012-11-29

Applicant: XILINX, INC.

Inventor： WU, Paul, Y.

IPC: H05K1/02

CPC classification number: H05K1/0221 ,  H05K1/0242 ,  H05K1/0251 ,  H05K2201/09672 ,  H05K2201/098 ,  H05K2201/09854

Abstract: An electrical circuit structure (100) can include a first trace (105) formed using a first conductive layer and a second trace (110) formed using a second conductive layer. The first trace can be vertically aligned with the second trace. The electrical circuit structure can include a via segment (115) formed of conductive material in a third conductive layer between the first conductive layer and the second conductive layer. The via segment can contact the first trace and the second trace forming a first conductor structure configured to convey an electrical signal in a direction parallel to the first conductive layer.

Abstract translation: 电路结构（100）可以包括使用第一导电层形成的第一迹线（105）和使用第二导电层形成的第二迹线（110）。 第一条迹线可以与第二条迹线垂直对齐。 电路结构可以包括在第一导电层和第二导电层之间的第三导电层中由导电材料形成的通孔段（115）。 通路段可以接触第一迹线和第二迹线，形成构造成在平行于第一导电层的方向上传送电信号的第一导体结构。

公开(公告)号：WO2012018415A1

公开(公告)日：2012-02-09

申请号：PCT/US2011/031371

申请日：2011-04-06

Applicant: XILINX, INC.

Inventor： KIM, Namhoon ,  KIM, Dong, W. ,  WU, Paul, Y.

IPC: H01L23/48 ,  H01L23/14 ,  H01L23/498

CPC classification number: H01L23/49827 ,  H01L23/147 ,  H01L23/481 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2224/0401

Abstract: A silicon substrate (201) has a conductive via (206) extending from a first surface (306) of the silicon substrate through the silicon substrate to a second surface (308) of the silicon substrate. A dielectric via (204,310) extends from the second surface of the silicon substrate toward the first surface of the silicon substrate.

Abstract translation: 硅衬底（201）具有从硅衬底的第一表面（306）穿过硅衬底延伸到硅衬底的第二表面（308）的导电通孔（206）。 电介质通孔（204,310）从硅衬底的第二表面延伸到硅衬底的第一表面。

公开(公告)号：WO2015153494A1

公开(公告)日：2015-10-08

申请号：PCT/US2015/023401

申请日：2015-03-30

Applicant: XILINX, INC.

Inventor： SHI, Hong ,  WU, Paul, Y. ,  LIU, Jian

IPC: H01L23/66 ,  H01L23/528 ,  H01L23/00

CPC classification number: H01L23/66 ,  H01L23/49827 ,  H01L24/16 ,  H01L2223/6627 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/19107

Abstract: Embodiments of the invention generally provide an electronic device (100) comprising an electrical interconnect component (1 12, 122, 136) that includes an electrical trace (501 (2)). The electrical trace (501 (2)) has geometric characteristics that serve to suppress the skin effect over a large band of frequency components. More specifically, the electrical trace (501 (2)) has a thickness that is less than a skin depth for a particular chosen frequency component. By making the electrical trace (501 (2)) have a thickness that is less than the skin depth, the current flows through substantially the entire cross- sectional area of the electrical trace (501 (2)) for all frequencies up to the chosen frequency component, which reduces the effects associated with the skin effect.

Abstract translation: 本发明的实施例通常提供一种电子设备（100），其包括包括电迹线（501（2））的电互连部件（112,122,136）。 电迹线（501（2））具有几何特征，其用于抑制频带分量的大频带上的皮肤效应。 更具体地，电迹线（501（2））具有小于特定选定频率分量的趋肤深度的厚度。 通过使电迹线（501（2））具有小于皮肤深度的厚度，电流流过所有频率的电迹线（501（2））的大致整个横截面积直到选定的 频率分量，减少与皮肤效应相关的影响。

公开(公告)号：WO2014151993A1

公开(公告)日：2014-09-25

申请号：PCT/US2014/026786

申请日：2014-03-13

Applicant: XILINX, INC.

Inventor： KIM, Namhoon ,  KIM, Joong-ho ,  RAMALINGAM, Suresh ,  WU, Paul, Y. ,  KWON, Woon-seong ,  LEUNG, Dennis, C.P.

IPC: H01L23/498 ,  H01L23/66

CPC classification number: H05K1/02 ,  H01L23/49822 ,  H01L23/66 ,  H01L2224/16225

Abstract: A multi-layer core organic package substrate (400) includes: a multi-layer core (409) comprising at least two organic core layers (41 1, 413), wherein two of the at least two organic core layers (41 1, 413) are separated by a core metal layer (401 ); a first plurality of build-up layers (207) formed on top of the multi-core layer (409); and a second plurality of build-up layers (207') formed below the multi-core layer (409).

Abstract translation: 多层核心有机封装基板（400）包括：多层芯（409），包括至少两个有机芯层（41 1，413），其中所述至少两个有机芯层（41 1，413）中的两个 ）由芯金属层（401）分离; 形成在所述多芯层（409）的顶部上的第一多个堆积层（207）; 以及形成在所述多芯层（409）下方的第二多个堆积层（207'）。

公开(公告)号：WO2011149561A1

公开(公告)日：2011-12-01

申请号：PCT/US2011/021471

申请日：2011-01-17

Applicant: XILINX, INC.

Inventor： WU, Paul, Y. ,  RAMALINGAM, Suresh ,  KIM, Namhoon

IPC: H01L23/48 ,  H01L21/768

CPC classification number: H01L21/76898 ,  H01L23/147 ,  H01L23/481 ,  H01L23/5384 ,  H01L25/0657 ,  H01L2223/6616 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/15311

Abstract: A device has a silicon substrate (302) with a via (300) extending from a first surface (312) of the silicon substrate having a conductor portion (304). A first dielectric portion (306) surrounds the conductor portion. A second dielectric portion (310) is disposed between a first silicon portion (308) and the silicon substrate (302).

Abstract translation: 器件具有硅衬底（302），其具有从具有导体部分（304）的硅衬底的第一表面（312）延伸的通孔（300）。 第一电介质部分（306）围绕导体部分。 第二电介质部分（310）设置在第一硅部分（308）和硅衬底（302）之间。

公开(公告)号：WO2013109340A1

公开(公告)日：2013-07-25

申请号：PCT/US2012/065185

申请日：2012-11-15

Applicant: XILINX, INC.

Inventor： KIM, Namhoon ,  KIM, Joong-ho ,  WU, Paul, Y. ,  RAMALINGAM, Suresh

IPC: H05K1/14 ,  H05K3/34

CPC classification number: H05K3/3436 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15788 ,  H01L2924/18161 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/147 ,  H05K2201/10189 ,  H05K2201/10378 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2924/00012

Abstract: An integrated circuit (IC) structure can include an internal element (110, 415, 410) and a flexible circuitry (140) directly coupled to the internal element. The flexible circuitry can be configured to exchange signals between the internal element and a node external to the IC structure (120, 455, 605, 615, 645).

Abstract translation: 集成电路（IC）结构可以包括直接耦合到内部元件的内部元件（110,415,410）和柔性电路（140）。 柔性电路可以被配置为在内部元件与IC结构外部的节点（120,455,605,615,645）之间交换信号。

公开(公告)号：WO2012078263A1

公开(公告)日：2012-06-14

申请号：PCT/US2011/058467

申请日：2011-10-28

Applicant: XILINX, INC.

Inventor： GHIA, Atul, V. ,  WYLAND, Christopher, P. ,  SODHA, Ketan ,  SASAKI, Paul, T. ,  TAN, Jian ,  WU, Paul, Y. ,  MAYDER, Romi

IPC: H01L23/528 ,  H01L23/522

CPC classification number: H01L23/5223 ,  H01L23/5286 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In one embodiment an integrated circuit (IC) is presented. The IC includes first and second sets of power distribution lines (204) formed in the IC. The IC includes first (210) and second (212) capacitors formed in one or more layers of the IC. A first plurality of vias (214) couple a first input of the first and second capacitors to the first set of power distribution lines, and a second plurality of vias (214) couple a second input of the first and second capacitors to the second set of power distribution lines. The first capacitor (210) and vias (214) coupled thereto having an equivalent series resistance greater than an equivalent series resistance of the second capacitor (210) and vias (214) coupled thereto.

Abstract translation: 在一个实施例中，呈现集成电路（IC）。 IC包括形成在IC中的第一组和第二组配电线（204）。 IC包括形成在IC的一个或多个层中的第一（210）和第二（212）电容器。 第一多个通孔（214）将第一和第二电容器的第一输入耦合到第一组配电线，以及第二多个通孔（214）将第一和第二电容器的第二输入端耦合到第二组 的配电线路。 耦合到其上的第一电容器（210）和通孔（214）具有大于第二电容器（210）的等效串联电阻和与其耦合的通孔（214）的等效串联电阻。

公开(公告)号：WO2011149567A1

公开(公告)日：2011-12-01

申请号：PCT/US2011/023440

申请日：2011-02-02

Applicant: XILINX, INC.

Inventor： HART, Michael, J. ,  DE JONG, Jan, L. ,  WU, Paul, Y.

IPC: H01L23/00 ,  H01L23/556

CPC classification number: H01L24/13 ,  H01L23/556 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/12 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05567 ,  H01L2224/1147 ,  H01L2224/11474 ,  H01L2224/1191 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/1355 ,  H01L2924/0002 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/36 ,  H01L2224/05552

Abstract: An embodiment of a method of forming a semiconductor device that includes a substrate (202) having an active layer (204) and interconnect (206) formed on the active layer is described. The method includes: forming a dielectric layer (210) above the interconnect (206) having a tapered via (604) exposing at least a portion of a first metal layer (216); forming an under-bump metallization (UBM) layer (218) over the tapered via and the first metal layer to form a UBM bucket (606); and forming a dielectric cap layer (212) over the dielectric layer and a portion of the UBM layer. The UBM bucket is configured to support a solder ball (214) and can advantageously block all alpha particles emitted by the solder ball having a relevant angle of incidence from reaching the active semiconductor regions of the IC. Thus, soft errors, such as single event upsets in memory cells, are reduced or eliminated.

Abstract translation: 描述形成半导体器件的方法的实施例，该半导体器件包括在有源层上形成的具有有源层（204）和互连（206）的衬底（202）。 该方法包括：在互连（206）之上形成具有暴露第一金属层（216）的至少一部分的锥形通孔（604）的介电层（210）; 在所述锥形通孔和所述第一金属层上形成凸起下金属化（UBM）层（218）以形成UBM桶（606）; 以及在介电层和UBM层的一部分上形成电介质盖层（212）。 UBM桶被配置为支撑焊球（214），并且可以有利地阻挡具有相关入射角的焊球发射的所有α粒子到达IC的有源半导体区域。 因此，减少或消除了诸如存储器单元中的单个事件的混乱的软错误。