公开(公告)号：WO2018183453A1

公开(公告)日：2018-10-04

申请号：PCT/US2018/024778

申请日：2018-03-28

Applicant: XILINX, INC.

Inventor： GANDHI, Jaspreet, Singh ,  RAMALINGAM, Suresh ,  LIU, Henley

IPC: H01L23/00

Abstract: Methods and apparatus are described for enabling copper-to-copper (Cu-Cu) bonding at reduced temperatures (e.g., at most 200°C) by significantly reducing Cu oxide formation. These techniques provide for faster cycle time and entail no extraordinary measures (e.g., forming gas). Such techniques may also enable longer queue (Q) or staging times. One example semiconductor structure (100) generally includes a semiconductor layer (102), an adhesion layer (104) disposed above the semiconductor layer (102), an anodic metal layer (106) disposed above the adhesion layer (104), and a cathodic metal layer (108) disposed above the anodic metal layer (106). An oxidation potential of the anodic metal layer (106) may be greater than an oxidation potential of the cathodic metal layer (108). Such a semiconductor structure (100) may be utilized in fabricating IC packages (300, 400) implementing 2.5D or 3D integration.

公开(公告)号：WO2014011281A1

公开(公告)日：2014-01-16

申请号：PCT/US2013/036212

申请日：2013-04-11

Applicant: XILINX, INC.

Inventor： KWON, Woon-Seong ,  RAMALINGAM, Suresh

IPC: H01L23/14 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L21/4853 ,  H01L23/147 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/75 ,  H01L24/81 ,  H01L24/97 ,  H01L25/0655 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/75744 ,  H01L2224/7598 ,  H01L2224/75983 ,  H01L2224/75987 ,  H01L2224/81005 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/3511 ,  H01L2924/014 ,  H01L2224/16225 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/81 ,  H01L2924/00014

Abstract: A method for flip chip stacking includes forming (201) a cavity wafer (301) comprising a plurality of cavities (303) and a pair of corner guides (305), placing (203) a through-silicon-via (TSV) interposer (103) with solder bumps (107) coupled to a surface of the TSV interposer on the cavity wafer, such that the solder bumps are situated in the plurality of cavities and the TSV interposer is situated between the pair of corner guides, placing (205) an integrated circuit (IC) die (109) on another surface of the TSV interposer, such that the IC die, the TSV interposer, and the solder bumps form a stacked interposer unit (113), removing (207) the stacked interposer unit from the cavity wafer, and bonding (209) the solder bumps of the stacked interposer unit to an organic substrate (101) such that the stacked interposer unit and the organic substrate form a flip chip (300).

Abstract translation: 一种用于倒装芯片堆叠的方法包括形成（201）包括多个空腔（303）和一对拐角引导件（305）的空腔晶片（301），放置（203）穿硅通孔（TSV）插入器 103），其中焊料凸块（107）耦合到空腔晶片上的TSV插入器的表面，使得焊料凸块位于多个空腔中，并且TSV插入件位于一对拐角引导件之间，放置（205） 在所述TSV插入器的另一表面上的集成电路（IC）管芯（109），使得所述IC管芯，所述TSV插入件和所述焊料凸块形成堆叠的中介层单元（113），将所述堆叠的中介层单元 将所述堆叠的中介层单元的所述焊料凸块接合（209）到有机基板（101），使得所述堆叠的中介层单元和所述有机基板形成倒装芯片（300）。

公开(公告)号：WO2021252037A2

公开(公告)日：2021-12-16

申请号：PCT/US2021/021235

申请日：2021-03-05

Applicant: XILINX, INC.

Inventor： REFAI-AHMED, Gamal ,  RAMALINGAM, Suresh ,  CHANG, Ken ,  RAJ, Mayank ,  XIE, Chuan ,  FRANS, Yohan

IPC: H01L23/367 ,  H01L23/40 ,  H01L25/16 ,  H01L23/473 ,  H01L2023/4056 ,  H01L2023/4075 ,  H01L23/3675 ,  H01L23/4006 ,  H01L25/167

Abstract: Some examples described herein provide for a heterogeneous integration module (HIM) that includes a thermal management apparatus. In an example, an apparatus (e.g., a HIM) includes a wiring substrate, a first component, a second component, and a thermal management apparatus. The first component and the second component are communicatively coupled together via the wiring substrate. The thermal management apparatus is in thermal communication with the first component and the second component. The thermal management apparatus has a first thermal energy flow path for dissipating thermal energy generated by the first component and has a second thermal energy flow path for dissipating thermal energy generated by the second component. The first thermal energy flow path has a lower thermal resistivity than the second thermal energy flow path.

公开(公告)号：WO2020006459A1

公开(公告)日：2020-01-02

申请号：PCT/US2019/039894

申请日：2019-06-28

Applicant: XILINX, INC

Inventor： PAN, Hong-Tsz ,  CHANG, Cheang-Whang ,  CHONG, Nui ,  LIU, Henley ,  REFAI-AHMED, Gamal ,  RAMALINGAM, Suresh

IPC: H01L23/367

Abstract: A method and apparatus are provided that includes an integrated circuit die 114, 116 having an in-chip heat sink 112, along with an electronic device and a chip package having the same, and methods for fabricating the same. In one example, an integrated circuit die 114, 116 has an in-chip heat sink 112 that separates a high heat generating integrated circuit device from another integrated circuit device disposed within the die 114, 116. The in-chip heat sink 112 provides a highly conductive heat transfer path from interior portions of the die 114, 116 to at least one exposed die surface.

公开(公告)号：WO2013109340A1

公开(公告)日：2013-07-25

申请号：PCT/US2012/065185

申请日：2012-11-15

Applicant: XILINX, INC.

Inventor： KIM, Namhoon ,  KIM, Joong-ho ,  WU, Paul, Y. ,  RAMALINGAM, Suresh

IPC: H05K1/14 ,  H05K3/34

CPC classification number: H05K3/3436 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15788 ,  H01L2924/18161 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/147 ,  H05K2201/10189 ,  H05K2201/10378 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2924/00012

Abstract: An integrated circuit (IC) structure can include an internal element (110, 415, 410) and a flexible circuitry (140) directly coupled to the internal element. The flexible circuitry can be configured to exchange signals between the internal element and a node external to the IC structure (120, 455, 605, 615, 645).

Abstract translation: 集成电路（IC）结构可以包括直接耦合到内部元件的内部元件（110,415,410）和柔性电路（140）。 柔性电路可以被配置为在内部元件与IC结构外部的节点（120,455,605,615,645）之间交换信号。

公开(公告)号：WO2021236350A1

公开(公告)日：2021-11-25

申请号：PCT/US2021/031211

申请日：2021-05-07

Applicant: XILINX, INC.

Inventor： GANDHI, Jaspreet Singh ,  RAMALINGAM, Suresh ,  ALLAIRE, William E. ,  SHI, Hong ,  PIERCE, Kerry M.

IPC: H01L25/18 ,  H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H01L23/538 ,  H01L21/56 ,  H01L23/433 ,  H01L21/683 ,  H01L23/31

Abstract: A chip package assembly and method for fabricating the same are provided that provide a modular chip stack that can be matched with one or more chiplets. The use of chiplets enables the same modular stack to be utilized in a large number of different chip package assembly designs, resulting much faster development times at a fraction of the overall solution cost.

公开(公告)号：WO2016153552A1

公开(公告)日：2016-09-29

申请号：PCT/US2015/054947

申请日：2015-10-09

Applicant: XILINX, INC.

Inventor： KWON, Woon-Seong ,  RAMALINGAM, Suresh

IPC: H01L25/065 ,  H01L25/07 ,  H01L25/00 ,  H01L23/488 ,  H01L23/498 ,  H01L23/00 ,  H01L23/538

CPC classification number: H01L25/0655 ,  H01L21/56 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/488 ,  H01L23/49816 ,  H01L23/5383 ,  H01L24/01 ,  H01L24/11 ,  H01L24/81 ,  H01L25/072 ,  H01L25/50 ,  H01L2224/11003 ,  H01L2224/16145 ,  H01L2224/1703 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/18161

Abstract: In one example, a semiconductor assembly comprises a first IC die (104A), a second IC die (104B), and a bridge module (110). The first IC die includes, on a top side thereof, first interconnects (108A) of a plurality of interconnects (108) and first inter-die contacts (608A) of a plurality of inter-die contacts (608). The second IC die includes, on a top side thereof, second interconnects (108B) of the plurality of interconnects and second inter-die contacts (608B) of the plurality of inter-die contracts. The bridge module is disposed between the first interconnects and the second interconnects and includes bridge interconnects (112) on a top side thereof, the bridge interconnects mechanically and electrically coupled to the plurality of inter-die contacts, and layer(s) of conductive interconnect (706) disposed on the top side thereof to route signals between the first IC and the second IC. A back side (710) of the bridge module does not extend beyond a height of the plurality of interconnects.

Abstract translation: 在一个示例中，半导体组件包括第一IC管芯（104A），第二IC管芯（104B）和桥接模块（110）。 第一IC芯片在其顶侧上包括多个互连（108）和多个晶片间接触（608）的第一晶片间触点（608A）的第一互连（108A）。 第二IC管芯在其顶侧上包括多个互连件中的第二互连（108B）和多个管芯间合同的第二管芯间接触（608B）。 桥模块设置在第一互连和第二互连之间，并且在其顶侧上包括桥互连（112），桥互连机械地和电耦合到多个管芯间接触和导电互连层 （706）设置在其顶侧，以在第一IC和第二IC之间路由信号。 桥模块的后侧（710）不延伸超出多个互连的高度。

公开(公告)号：WO2016032804A1

公开(公告)日：2016-03-03

申请号：PCT/US2015/045752

申请日：2015-08-18

Applicant: XILINX, INC.

Inventor： KWON, Woon-Seong ,  RAMALINGAM, Suresh

IPC: H01L25/065 ,  H01L23/485 ,  H01L25/00

CPC classification number: H01L23/5383 ,  H01L21/6835 ,  H01L23/16 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5384 ,  H01L24/17 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/071 ,  H01L25/50 ,  H01L2221/68345 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81005 ,  H01L2224/83005 ,  H01L2224/92125 ,  H01L2225/06517 ,  H01L2924/07802 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/00012

Abstract: Examples generally provide a stacked silicon interconnect product (109) and method of manufacture. The stacked silicon interconnect product (109) includes a silicon substrate-less interposer (102) comprising a plurality of metallization layers (104), wherein at least one metallization layer (104) includes a plurality of metal segments (106) separated by dielectric material (108). The stacked silicon interconnect product (109) also includes a first die (110) coupled to a first side of the silicon substrate-less interposer (102) via a first plurality of microbumps (114). The stacked silicon interconnect product (109) further includes a second die (112) coupled to a second side of the silicon substrate-less interposer (102) via a second plurality of microbumps (114), the second die (112) communicatively coupled to the first die (110) through a metallization layer (104) of the plurality of metallization layers (104).

Abstract translation: 实例通常提供堆叠的硅互连产品（109）和制造方法。 堆叠的硅互连产品（109）包括包括多个金属化层（104）的无硅衬底中介层（102），其中至少一个金属化层（104）包括由电介质材料分离的多个金属段（106） （108）。 堆叠的硅互连产品（109）还包括通过第一多个微胶片（114）耦合到无硅衬底的插入件（102）的第一侧的第一裸片（110）。 堆叠的硅互连产品（109）还包括经由第二多个微焦点（114）耦合到无硅衬底的中介层（102）的第二侧的第二裸片（112），所述第二裸片（112）可通信地耦合到 所述第一管芯（110）穿过所述多个金属化层（104）的金属化层（104）。

公开(公告)号：WO2015120196A1

公开(公告)日：2015-08-13

申请号：PCT/US2015/014685

申请日：2015-02-05

Applicant: XILINX, INC.

Inventor： WU, Paul, Y. ,  NIAZI, Sarajuddin ,  ANDERSON, Raymond, E. ,  RAMALINGAM, Suresh

IPC: H01L23/538

CPC classification number: H01R12/71 ,  H01L23/49816 ,  H01L23/5385 ,  H01L23/5386 ,  H01L2224/16 ,  H01L2924/0002 ,  H01R43/0235 ,  Y10T29/49117 ,  H01L2924/00

Abstract: An apparatus for placement between a package and an integrated circuit board is provided. The apparatus may include: an insert (112). The insert may have: a substrate having a top side and a bottom side; a first set of pads (114) at the top side of the substrate; a second set of pads (114) at the bottom side of the substrate; and a plurality of vias (116) in the substrate, the vias (116) connecting respective pads (114) in the first set to respective pads (114) in the second set; wherein the insert (112) has a thickness that is less than a spacing between the package and the integrated circuit board.

Abstract translation: 提供一种用于放置在封装和集成电路板之间的装置。 该装置可以包括：插入件（112）。 插入件可以具有：具有顶侧和底侧的基板; 在衬底的顶侧的第一组焊盘（114）; 在衬底的底侧的第二组衬垫（114）; 和多个通孔（116），所述通孔（116）将第一组中的相应衬垫（114）连接到第二组中的相应衬垫（114）; 其中插入件（112）的厚度小于封装和集成电路板之间的间隔。

公开(公告)号：WO2019199436A1

公开(公告)日：2019-10-17

申请号：PCT/US2019/023894

申请日：2019-03-25

Applicant: XILINX, INC.

Inventor： SHI, Hong ,  RAMALINGAM, Suresh ,  TAN, Siow Chek ,  REFAI-AHMED, Gamal

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L25/065 ,  H01L23/433

Abstract: Examples of the present disclosure provide example Chip Scale Packages (CSPs). In some examples, a structure Includes a first integrated circuit die (24), a shim die (28, 28A) that does not include active circuitry thereon, an encapsulant (40) at least laterally encapsulating the first integrated circuit die (24) and the shim die (28, 28A), and a redistribution structure (50) on the first integrated circuit die (24), the shim die (28, 28A), and the encapsulant (40). The redistribution structure (50) includes one or more metal layers (54) electrically connected to the first integrated circuit die (24).