公开(公告)号：EP2571045B1

公开(公告)日：2016-05-25

申请号：EP12173326.5

申请日：2012-06-25

申请人： COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

发明人： Marion, François

IPC分类号： H01L21/56 ,  H01L23/24 ,  H01L23/043 ,  H01L23/053 ,  H01L23/31 ,  H01L21/98 ,  H01L25/065

CPC分类号： H01L21/563 ,  B81C1/00293 ,  B81C2203/0118 ,  B81C2203/0145 ,  H01L21/56 ,  H01L23/043 ,  H01L23/053 ,  H01L23/24 ,  H01L23/3121 ,  H01L23/3128 ,  H01L2224/73203 ,  H01L2924/12044 ,  H01L2924/1461 ,  H01L2924/00

公开(公告)号：EP2916384A1

公开(公告)日：2015-09-09

申请号：EP13850263.8

申请日：2013-06-25

申请人： NEC Corporation

发明人： KUWABARA, Toshihide

IPC分类号： H01P5/107 ,  H01L23/12

CPC分类号： H01P5/107 ,  H01L23/043 ,  H01L23/12 ,  H01L23/15 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/66 ,  H01L24/48 ,  H01L2223/6627 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/1423 ,  H01L2924/15156 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package mounting structure includes a substrate (200) and a semiconductor package (100). The substrate (200) includes an opening (210) connected to a cavity of a waveguide (310). The semiconductor package (100) is mounted on the substrate (200). The semiconductor package (100) includes a semiconductor device (110) and a probe (152) connected to the semiconductor device (110). The opening (210) includes a part that overlaps the probe (152) and a part that does not overlap the semiconductor package (100).

摘要翻译： 半导体封装安装结构包括衬底（200）和半导体封装（100）。 衬底（200）包括连接到波导（310）的空腔的开口（210）。 半导体封装（100）安装在基板（200）上。 半导体封装（100）包括连接到半导体器件（110）的半导体器件（110）和探针（152）。 开口（210）包括与探针（152）重叠的部分和不与半导体封装（100）重叠的部分。

公开(公告)号：EP2851950A4

公开(公告)日：2015-07-15

申请号：EP13790413

申请日：2013-05-07

申请人： PANASONIC IP MAN CO LTD

发明人： YAMASHITA KENYA

IPC分类号： H01L25/07 ,  H01L23/00 ,  H01L23/495 ,  H01L23/498 ,  H01L25/18

CPC分类号： H01L23/49548 ,  H01L23/043 ,  H01L23/24 ,  H01L23/28 ,  H01L23/34 ,  H01L23/3735 ,  H01L23/4334 ,  H01L23/49517 ,  H01L23/49534 ,  H01L23/49537 ,  H01L23/49541 ,  H01L23/49575 ,  H01L23/49589 ,  H01L23/49811 ,  H01L24/32 ,  H01L24/37 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/07 ,  H01L25/18 ,  H01L27/0629 ,  H01L2224/32245 ,  H01L2224/37124 ,  H01L2224/37147 ,  H01L2224/40247 ,  H01L2224/45014 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/48145 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/4903 ,  H01L2224/73221 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/85001 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01015 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/30107 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/01005 ,  H01L2224/84

摘要： Included are: the first frame (1) and the second frame (2) where the plural transistor chips (1) and diode chips (12) are arranged; the first intermediate frame (5) which is adjacent to the first frame; the second intermediate frame (6) which is adjacent to the second frame; the third frame (3) which is electrically connected to the first intermediate frame and is arranged above the first frame; the fourth frame (4) which is electrically connected to the second intermediate frame and is arranged above the second frame; the electric source terminal part (22) which is provided on an extension of the first frame; the ground terminal part (23) which is provided on an extension of the fourth frame; and the output terminal part (24) which is provided on an extension to which the second frame and the third frame are electrically joined, wherein the third frame (3) and the fourth frame (4) are arranged in parallel with each other, and the electric source terminal part, the ground terminal part and the output terminal part are arranged in a manner such that induced electric voltages, which are generated in the third frame (3) and the fourth frame (4), become in reverse directions with each other.

公开(公告)号：EP2814060A1

公开(公告)日：2014-12-17

申请号：EP13803451.7

申请日：2013-04-16

申请人： Fuji Electric Co., Ltd.

发明人： DENTA, Toshio ,  SEKI, Tomonori ,  YAMADA, Tadanori ,  SATO, Tadahiko

IPC分类号： H01L25/07 ,  H01L25/18

CPC分类号： H01L25/18 ,  H01L23/043 ,  H01L23/24 ,  H01L23/3735 ,  H01L23/495 ,  H01L23/49517 ,  H01L23/49575 ,  H01L23/49811 ,  H01L23/49833 ,  H01L23/49861 ,  H01L23/50 ,  H01L24/48 ,  H01L24/49 ,  H01L25/162 ,  H01L2224/48091 ,  H01L2224/48101 ,  H01L2224/48105 ,  H01L2224/48137 ,  H01L2224/48139 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2224/49107 ,  H01L2924/00014 ,  H01L2924/1203 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

摘要： A main circuit wiring pattern (4) formed on an insulating layer (3) of a main circuit substrate (1) is bonded with rear surfaces of semiconductor chips (5, 6) constituting a main circuit (10a) by a bonding material, such as solder. Front surface electrodes of the semiconductor chips (5, 6) are electrically connected to lead terminals (13a) used for power by bonding wires (11) having a relatively wide diameter. The rear surface of a control semiconductor chip (9) constituting a control circuit (10b) is bonded with a control circuit wiring pattern (8b) on a control circuit substrate (7) constituted by a bottom surface portion (12-1) of a case (12), which is bonded to a rim of the main circuit substrate (1), by a bonding material. A principal surface of the control circuit substrate (7) is located at a higher position than a principal surface of the main circuit substrate (1) so that a step is formed between these principal surfaces. Whereby, a semiconductor device, which excels in noise suppression and has a structure that can be manufactured with fewer manufacturing steps and at lower cost, can be provided.

摘要翻译： 形成在主电路基板（1）的绝缘层（3）上的主电路布线图案（4）通过接合材料与构成主电路（10a）的半导体芯片（5,6）的背面接合， 作为焊料。 半导体芯片（5,6）的正面电极通过键合直径相对较宽的导线（11）电连接到用于供电的引线端子（13a）。 构成控制电路（10b）的控制用半导体芯片（9）的背面在控制电路用基板（7）上与控制电路用配线图案（8b）接合，所述控制电路用基板由下述 （12），其通过接合材料接合到主电路基板（1）的边缘。 控制电路基板（7）的主面位于比主电路基板（1）的主面高的位置，在这些主面之间形成台阶。 由此，可以提供一种半导体器件，该半导体器件具有优异的噪声抑制能力，并且具有可以用更少的制造步骤和更低的成本制造的结构。

公开(公告)号：EP2608260A2

公开(公告)日：2013-06-26

申请号：EP12179960.5

申请日：2012-08-09

申请人： Raytheon Company

发明人： Rajendran, S. ,  Sanchez, Monte R. ,  Eshelman, Susan M. ,  Gentry, Douglas R. ,  Hanft, Thomas A.

IPC分类号： H01L23/538 ,  H01L23/544

CPC分类号： H01L23/142 ,  H01L23/043 ,  H01L23/13 ,  H01L23/36 ,  H01L23/3736 ,  H01L23/488 ,  H01L23/5389 ,  H01L23/544 ,  H01L24/19 ,  H01L24/20 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L24/92 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54473 ,  H01L2224/02379 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/2105 ,  H01L2224/211 ,  H01L2224/214 ,  H01L2224/215 ,  H01L2224/2731 ,  H01L2224/27334 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/29116 ,  H01L2224/29294 ,  H01L2224/29339 ,  H01L2224/32245 ,  H01L2224/8313 ,  H01L2224/83132 ,  H01L2224/83815 ,  H01L2224/8385 ,  H01L2224/83851 ,  H01L2224/83862 ,  H01L2224/92244 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13064 ,  H01L2924/00014 ,  H01L2924/01082 ,  H01L2924/01049 ,  H01L2924/01079 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/00

摘要： Integrating a semiconductor component with a substrate through a low loss interconnection formed through adaptive patterning includes forming a cavity in the substrate, placing the semiconductor component therein, filling a gap between the semiconductor component and substrate with a fill of same or similar dielectric constant as that of the substrate and adaptively patterning a low loss interconnection on the fill and extending between the contacts of the semiconductor component and the electrical traces on the substrate. The contacts and leads are located and adjoined using an adaptive patterning technique that places and forms a low loss radio frequency transmission line that compensates for any misalignment between the semiconductor component contacts and the substrate leads.

摘要翻译： 通过自适应图案形成的低损耗互连将半导体元件与衬底集成，包括在衬底中形成空腔，将半导体元件放置在其中，用与之相同或相似的介电常数的填充填充半导体元件与衬底之间的间隙 并且自适应地对填充物上的低损耗互连进行图案化并且在半导体部件的触点与衬底上的电迹线之间延伸。 触点和引线使用自适应图案化技术来定位和邻接，所述自适应图案化技术放置并形成低损耗射频传输线，其补偿半导体部件触点和衬底引线之间的任何未对准。

公开(公告)号：EP0181975B1

公开(公告)日：1989-03-29

申请号：EP84307918.7

申请日：1984-11-15

申请人： FUJI ELECTRIC CO., LTD.

发明人： Nihei, Kazuya

IPC分类号： H01L23/14

CPC分类号： H01L23/142 ,  H01L23/043 ,  H01L23/49562 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/45124 ,  H01L2224/48091 ,  H01L2224/49111 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/1301 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2224/05599

摘要： A transistor chip (1) is secured directly on to a metal plate (2), the collector of the transistor chip making direct electrical contact with the plate (2). In order to minimise the area of the plate (2) the emitter terminal (6) is arranged to overlie the collector terminal (7) with an intervening ceramic insulating layer (3). The base terminal (4) is separated from the other terminals by the chip (1) and is secured to an insulating layer (3) which in turn is secured to the plate (2). All the terminals have upright extensions for providing external connection. The device is normally enclosed in a resin material except for connecting portions of the upright terminal extensions.

公开(公告)号：EP0109899B1

公开(公告)日：1987-04-15

申请号：EP83402201.4

申请日：1983-11-15

申请人： THOMSON-CSF

发明人： Heitzmann, Michel ,  Boudot, Marianne

IPC分类号： H01L23/56 ,  H01L23/04

CPC分类号： H01L23/66 ,  H01L23/043 ,  H01L2224/32188 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12032 ,  H01L2924/3011 ,  H01L2924/00

公开(公告)号：EP0089898A2

公开(公告)日：1983-09-28

申请号：EP83400588.6

申请日：1983-03-22

申请人： THOMSON-CSF

发明人： Heitzmann, Michel ,  Boudot, Marianne

IPC分类号： H01L23/56 ,  H01L23/04

CPC分类号： H01L23/043 ,  H01L23/66 ,  H01L2224/32188 ,  H01L2924/01057 ,  H01L2924/01079 ,  H01L2924/12032 ,  H01L2924/3011 ,  H01L2924/00

摘要： L'invention concerne un montage de diode hyperfréquence, en vue de réaliser un module préadapté.
Le module selon l'invention comprend une embase (3) en cuivre, un anneau de quartz (6) et un capot (11) en cuivre : ces trois pièces, dorées au moins sur leurs faces en regard, sont assemblées par thermocompression (12,13). A l'intérieur de ce boitier, la pastille de diode (4), soudée sur l'embase (3) par l'intermédiaire d'un radiateur d'or (9) est polarisée par une connexion en faux "beam-lead" (10), étoile métallique dont les branches sont incurvées, ce qui diminue l'inductance et la capacité de cette connexion par rapport à l'embase. Le faux "beam-lead" est réalisé par métallisation d'un mésa obtenu sur une tranche de silicium.
Application aux systèmes fonctionnant en hyperfréquences, notamment dans le domaine des hyperfréquences.

公开(公告)号：EP3648154B1

公开(公告)日：2024-09-18

申请号：EP19216618.9

申请日：2011-11-08

IPC分类号： H01L23/04 ,  H01L23/16 ,  H01L23/043 ,  H01L23/047 ,  H01L23/053 ,  H01L23/057 ,  H01L23/10 ,  H01L23/15 ,  G06F1/16 ,  G06F1/18

CPC分类号： G06F1/181 ,  H01L23/043 ,  H01L23/047 ,  H01L23/053 ,  H01L23/057 ,  H01L23/10 ,  H01L2924/000220130101 ,  Y10T29/302 ,  Y10T29/49826 ,  Y10T29/49002 ,  H01L23/16 ,  H01L23/04

公开(公告)号：EP3203515A4

公开(公告)日：2018-05-30

申请号：EP15846216

申请日：2015-09-16

申请人： SANSHA ELECTRIC MFG CO LTD

发明人： TAKAMURA AKIO

IPC分类号： H01L25/07 ,  H01L23/04 ,  H01L23/48 ,  H01L23/50

CPC分类号： H01L23/049 ,  H01L23/04 ,  H01L23/041 ,  H01L23/043 ,  H01L23/053 ,  H01L23/08 ,  H01L23/10 ,  H01L23/24 ,  H01L23/28 ,  H01L23/48 ,  H01L23/492 ,  H01L23/50 ,  H01L23/562 ,  H01L25/0655 ,  H01L25/07 ,  H01L25/072 ,  H01L25/18 ,  H01L2924/0002 ,  H01L2924/00

摘要： Sought is to provide a semiconductor module that makes it possible to easily perform visual observation of soldering, and to perform a reflow soldering process in a state where external terminals are attached to a case. A semiconductor module includes a rectangular base plate; a substrate which is placed on the base plate and on which a circuit including a semiconductor chip and so forth is formed; a rectangular parallelepiped case made of resin that is attached to the base plate and houses the substrate within; and a plurality of external terminals lower ends of which are fixed to the substrate with upper ends thereof being exposed on a top face of the case. The case is provided with a first case opening portion and a second case opening portion that are respectively formed by cutting off a front face and a rear face of the case from an upper edge thereof along a longitudinal direction thereof; and the top face of the case between the first case opening portion and the second case opening portion includes an external terminal holding portion to hold the plurality of external terminals along the longitudinal direction with the upper ends thereof being exposed. A sealing material is injected from the first case opening portion and the second case opening portion onto a top face of the substrate, and thereby the semiconductor module is sealed.