利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

1380 条记录 (耗时 0.024 秒)

    Programmable acquisition module for multi-standard CDMA based receivers
    92.
    发明公开
    Programmable acquisition module for multi-standard CDMA based receivers 审中-公开
    多标准执行者程序员

    公开(公告)号：EP1441449A1

    公开(公告)日：2004-07-28

    申请号：EP03250482.1

    申请日：2003-01-27

    申请人： Agilent Technologies, Inc. - a Delaware corporation -

    发明人： Lugil, Nico

    IPC分类号： H04B1/707

    CPC分类号： H04B1/70775 ,  H04B2201/70711

    摘要： The present invention is related to a Programmable Acquisition Module for the acquisition of synchronisation signals in a spread-spectrum communication system, comprising

    a matched filter with programmable length (1)
    accumulator with RAM (3), using input either directly from said matched filter or via the first energy calculation block
    hardware synchronisation counter (7) that supports the SW such that the HW acquisition process can be started at precise defined moments
    a dwell counter (8)
    an address generator (4)
       all arranged for control or programming by a software controller,

    a first energy calculation block (2)
    a second energy calculation block (5) to calculate the energy of the accumulated values
    a maximum finder block (6) to find the maximum energy value of the accumulated values,
    whereby the accumulator (3), connected with the matched filter (1) both directly and via the energy calculation block (2), is arranged for getting inputs from the address generator and the software controller,
        characterised in that the module is configurable for the acquisition of

    codes with a length up to the matched filter's maximum length with non-coherent dwell,
    codes with a length up to the matched filter's maximum length with coherent dwell, and
    codes with a length larger than the matched filter's maximum length.

    摘要翻译： 本发明涉及一种用于在扩展频谱通信系统中获取同步信号的可编程采集模块，该可编程采集模块包括具有可编程长度（1）累加器与RAM（3）的匹配滤波器，使用直接来自所述匹配滤波器的输入或 通过支持SW的第一能量计算块硬件同步计数器（7），使得可以在精确定义的时刻开始HW获取过程，驻留计数器（8）全部被布置用于由软件控制或编程的地址生成器（4） 控制器，第一能量计算块（2）计算积累值的能量的第二能量计算块（5），用于找到累积值的最大能量值的最大取景器块（6），由此累加器（3） 通过直接和通过能量计算块（2）与匹配滤波器（1）连接，被布置成用于从地址发生器和软件连接 辊，其特征在于，该模块可配置用于以非相干驻留的长度达到匹配滤波器的最大长度的代码获取，其长度高达匹配滤波器的最大长度，具有相干驻留，并且具有长度 大于匹配滤镜的最大长度。

    Method and device for injecting a pilot tone into a digital signal
    95.
    发明公开
    Method and device for injecting a pilot tone into a digital signal 有权
    Verfahren undGerätzum Einkoppeln eine Pilottons in ein Digitalsignal

    公开(公告)号：EP1439644A1

    公开(公告)日：2004-07-21

    申请号：EP03250217.1

    申请日：2003-01-14

    申请人： Agilent Technologies, Inc. - a Delaware corporation -

    发明人： Cerisola, Mauro, Agilent Technologies Italia

    IPC分类号： H04B10/155 ,  H04B10/08

    CPC分类号： H04B10/0775 ,  H04B2210/075

    摘要： The power of a digital signal such as an optical data stream is set via digital-to-analog converter (12) having a reference input (12a) for connection to a DC reference signal (14). The pilot tone is injected into the reference input (12a) of the digital-to-analog converter. In the place of a dual amplitude control (modulation current and pilot tone), the arrangement of the invention only requires a single control, thereby reducing cost, power consumption, microcontroller input/output activity, area occupation (PCB real estate) and failure rate.

    摘要翻译： 通过具有用于连接到DC参考信号（14）的参考输入（12a）的数模转换器（12）来设置数字信号（诸如光数据流）的功率。 导频音被注入到数模转换器的参考输入（12a）中。 在双幅度控制（调制电流和导频音）的地方，本发明的布置仅需要单一控制，从而降低成本，功耗，微控制器输入/输出活动，区域占用（PCB空间）和故障率 。

    Process for etching heterojunction interfaces and corresponding layer structures
    96.
    发明公开
    Process for etching heterojunction interfaces and corresponding layer structures 审中-公开
    的蚀刻接口在异质结和相应的层结构的方法

    公开(公告)号：EP1174913A3

    公开(公告)日：2004-07-14

    申请号：EP01110433.8

    申请日：2001-04-27

    申请人： Agilent Technologies, Inc. (a Delaware corporation)

    发明人： Bahl, Sandeep R. ,  Houng, Yu-Min ,  Robbins, Virginia M. ,  Sugihwo, Fred

    IPC分类号： H01L21/306

    CPC分类号： H01L21/3065 ,  Y10T428/12528 ,  Y10T428/12681

    摘要： Systems and methods of manufacturing etchable heterojunction interfaces and etched heterojunction structures are described. A bottom layer (14) is deposited on a substrate (16), a transition etch layer (20) is deposited over the bottom layer (14), and a top layer (12) is deposited over the transition etch layer (20). The transition etch layer (20) substantially prevents the bottom layer (14) and the top layer (12) from forming a material characterized by a composition substantially different than the bottom layer (14) and a substantially non-selective etchability with respect to the bottom layer (14). By tailoring the structure of the heterojunction interface to respond to heterojunction etching processes with greater predictability and control, the transition etch layer (20) enhances the robustness of previously unreliable heterojunction device manufacturing processes. The transition etch layer (20) enables one or more vias (72) to be etched down to the top surface of the bottom layer (14) in a reliable and repeatable manner. In particular, because the transition etch layer (20) enables use of an etchant that is substantially selective with respect to the bottom layer (14), the thickness of critical device layers may be determined by the precise epitaxial growth processes used to form the bottom layer (14) rather than relatively imprecise non-selective etch processes.