公开(公告)号：EP2105966B1

公开(公告)日：2017-08-23

申请号：EP09006485.8

申请日：2000-05-11

申请人： Semiconductor Energy Laboratory Co, Ltd.

发明人： Kokubo, Chiho ,  Yamagata, Hirokazu ,  Yamazaki, Shunpei

IPC分类号： H01L27/12 ,  H01L29/786 ,  H01L29/66 ,  H01L21/20 ,  G02F1/1345 ,  G09G3/3225 ,  G09G3/3233 ,  H01L29/04 ,  G09G3/30 ,  G09G3/36 ,  H01L27/32

CPC分类号： H01L21/02672 ,  G02F1/13454 ,  G09G3/30 ,  G09G3/3225 ,  G09G3/3233 ,  G09G3/3648 ,  G09G2300/0842 ,  G09G2300/0861 ,  H01L21/02532 ,  H01L21/2022 ,  H01L27/12 ,  H01L27/1248 ,  H01L27/1255 ,  H01L27/1277 ,  H01L27/3244 ,  H01L29/04 ,  H01L29/66757 ,  H01L29/78624 ,  H01L29/78645 ,  H01L29/78675

摘要： There is disclosed a semiconductor device and a method of fabricating the semiconductor device in which a heat treatment time required for crystal growth is shortened and a process is simplified. Two catalytic element introduction regions are arranged at both sides of one active layer and crystallization is made. A boundary portion where crystal growth from one catalytic element introduction region meets crystal growth from the other catalytic element introduction region is formed in a region which becomes a source region or drain region.

摘要翻译： 公开了一种半导体器件和制造半导体器件的方法，其中晶体生长所需的热处理时间缩短并且工艺简化。 两个催化元素引入区布置在一个有源层的两侧并进行结晶化。 在成为源极区域或漏极区域的区域形成来自一个催化剂元素导入区域的晶体生长与来自另一个催化剂元素导入区域的晶体生长的边界部分。

公开(公告)号：EP3185303A1

公开(公告)日：2017-06-28

申请号：EP16160174.5

申请日：2016-03-14

申请人： IMEC VZW ,  Katholieke Universiteit Leuven

发明人： Pourtois, Geoffrey ,  Lu, Anh Khoa Augustin ,  Huyghebaert, Cedric

IPC分类号： H01L29/778 ,  H01L29/40 ,  H01L29/78 ,  H01L29/24 ,  H01L29/16

CPC分类号： H01L29/66977 ,  H01L29/16 ,  H01L29/24 ,  H01L29/402 ,  H01L29/778 ,  H01L29/7831 ,  H01L29/78645 ,  H01L29/78681 ,  H01L29/78684 ,  H01L29/78696

摘要： A semiconductor device is disclosed comprising a two-dimensional (2D) material layer, the 2D material layer comprising a channel region in between a source region and a drain region; a first gate stack and a second gate stack in contact with the 2D material layer, the first and second gate stack being spaced apart over a distance; the first gate stack located on the channel region of the 2D material layer and in between the source region and the second gate stack, the first gate stack arranged to control the injection of carriers from the source region to the channel region and the second gate stack located on the channel region of the 2D material layer; the second gate stack arranged to control the conduction of the channel region.

摘要翻译： 公开了一种包括二维（2D）材料层的半导体器件，该2D材料层包括位于源极区和漏极区之间的沟道区; 与所述2D材料层接触的第一栅极叠层和第二栅极叠层，所述第一和第二栅极叠层间隔开一段距离; 所述第一栅叠层位于所述2D材料层的所述沟道区上并且位于所述源区和所述第二栅叠层之间，所述第一栅叠层设置成控制载流子从所述源区到所述沟道区的注入以及所述第二栅叠层 位于2D材料层的沟道区上; 第二栅极叠层被安排成控制沟道区域的导电。

公开(公告)号：EP2500941A3

公开(公告)日：2017-05-10

申请号：EP12172007.2

申请日：2000-05-31

申请人： Semiconductor Energy Laboratory Co., Ltd.

发明人： Yamazaki, Shunpei ,  Suzawa, Hideomi ,  Yamagata, Hirokazu

IPC分类号： H01L29/786 ,  H01L29/66 ,  H01L29/45 ,  H01L29/49

CPC分类号： H01L29/78621 ,  G02F1/13454 ,  H01L27/124 ,  H01L27/1248 ,  H01L27/1255 ,  H01L27/3244 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/66757 ,  H01L29/66765 ,  H01L29/78645 ,  H01L29/78675 ,  H01L29/78678 ,  H01L2924/0002 ,  H01L2924/00

摘要： The invention provides a semiconductor device comprising a transistor; a first interlayer insulating film over the transistor; a second interlayer insulating film over the first interlayer insulating film; and a conductive layer over the second interlayer insulating film, wherein the second interlayer insulating film covers a gate electrode of the transistor, and is selectively removed over a contact portion between a semiconductor layer of the transistor and the conductive layer, wherein the conductive layer is electrically connected to the semiconductor layer through a hole opened in the first interlayer insulating film, and wherein the conductive layer partly or entirely overlaps the gate electrode with the first interlayer insulating film and the second interlayer insulating film interposed therebetween.

摘要翻译： 为了增加孔径比，使与像素TFT的沟道形成区域（213,214）重叠的栅电极的一部分或全部与第二布线（源极线或漏极线）（154,157）重叠 ）。 此外，第一层间绝缘膜（149）和第二层间绝缘膜（150c）设置在栅电极和第二布线（154,157）之间，以便降低寄生电容。

公开(公告)号：EP2276067B1

公开(公告)日：2017-05-10

申请号：EP10012827.1

申请日：2001-02-02

申请人： Semiconductor Energy Laboratory Co, Ltd.

发明人： Fukunaga, Takeshi ,  Maruyama, Junya

IPC分类号： H01L29/786 ,  H01L27/32 ,  H01L51/52 ,  H01L27/12

CPC分类号： H01L27/3276 ,  H01L27/12 ,  H01L27/1214 ,  H01L27/1288 ,  H01L27/15 ,  H01L27/3211 ,  H01L27/3244 ,  H01L27/3246 ,  H01L27/3248 ,  H01L27/3262 ,  H01L27/3295 ,  H01L29/78645 ,  H01L29/78669 ,  H01L51/0097 ,  H01L51/5206 ,  H01L51/5218 ,  H01L51/5228 ,  H01L51/5234 ,  H01L51/5237 ,  H01L51/525 ,  H01L51/5271 ,  H01L51/56 ,  H01L2251/5315 ,  Y10S428/917

公开(公告)号：EP2104950B1

公开(公告)日：2016-11-16

申请号：EP07858218.6

申请日：2007-12-28

申请人： Commissariat à l'Énergie Atomique et aux Énergies Alternatives

发明人： VINET, Maud ,  THOMAS, Olivier ,  ROZEAU, Olivier ,  POIROUX, Thierry

IPC分类号： H01L27/11 ,  H01L21/8244

CPC分类号： H01L27/1104 ,  G11C11/412 ,  H01L27/11 ,  H01L29/78645

公开(公告)号：EP3070746A1

公开(公告)日：2016-09-21

申请号：EP15866397.1

申请日：2015-11-10

申请人： BOE Technology Group Co., Ltd.

发明人： SHI, Lei ,  XU, Xiaowei

IPC分类号： H01L29/786 ,  H01L21/28

CPC分类号： H01L29/78648 ,  H01L21/02532 ,  H01L21/02565 ,  H01L21/02592 ,  H01L21/02595 ,  H01L21/02675 ,  H01L21/0273 ,  H01L21/266 ,  H01L21/28 ,  H01L21/426 ,  H01L27/1218 ,  H01L27/1222 ,  H01L27/1225 ,  H01L27/1274 ,  H01L29/6675 ,  H01L29/66969 ,  H01L29/78603 ,  H01L29/78618 ,  H01L29/78645 ,  H01L29/78672 ,  H01L29/7869

摘要： Embodiments of the present disclosure provide an array substrate, a method for producing the same and a display device including the same. The array substrate includes a substrate; a first gate, a first gate insulation layer, an active layer, a second gate insulation layer, a second gate, a third gate insulation layer and source and drain electrodes provided on the substrate in sequence. Two side regions outside a region of the active layer corresponding to the second gate are source and drain-lightly doped regions and source and drain-heavily doped regions, respectively. The source and drain electrodes are contacted and connected with the heavily doped source and drain regions, respectively. The first gate is provided below the lightly doped drain region corresponding to the drain electrode, or the first gate includes a first sub part and a second sub part which are respectively provided below the lightly doped source and drain regions corresponding to the source and drain electrodes respectively.

摘要翻译： 本发明实施例提供了一种阵列基板及其制作方法以及包括该阵列基板的显示装置。 阵列基板包括基板; 第一栅极，第一栅极绝缘层，有源层，第二栅极绝缘层，第二栅极，第三栅极绝缘层以及依次设置在衬底上的源极和漏极。 在对应于第二栅极的有源层区域之外的两个侧面区域分别是源极和漏极轻掺杂区域以及源极和漏极重度掺杂区域。 源电极和漏电极分别与重掺杂源极区和漏极区接触并连接。 第一栅极设置在对应漏极的轻掺杂漏极区的下方，或者第一栅极包括第一子部分和第二子部分，第一子部分和第二子部分分别设置在对应于源极和漏极的轻掺杂源极和漏极区的下方 分别。

公开(公告)号：EP3015833A1

公开(公告)日：2016-05-04

申请号：EP14191383.0

申请日：2014-10-31

申请人： Nokia Technologies OY

发明人： Colli, Alan

IPC分类号： G01J5/04 ,  G01J5/34

CPC分类号： H01L31/113 ,  G01J5/046 ,  G01J5/10 ,  G01J5/34 ,  H01L21/041 ,  H01L29/1606 ,  H01L29/404 ,  H01L29/4238 ,  H01L29/42384 ,  H01L29/778 ,  H01L29/78603 ,  H01L29/78645 ,  H01L29/78684 ,  H01L29/78696 ,  H01L31/035218 ,  H01L31/119

摘要： An apparatus comprising: pyroelectric material; an electric field sensor; a first conductive electrode comprising a first area adjacent the pyroelectric material; a second conductive electrode comprising a second area adjacent the electric field sensor; and a conductive interconnection between the first conductive electrode and the second conductive electrode, wherein the first area of the first conductive electrode is larger than the second area of the second conductive electrode.

摘要翻译： 一种装置，包括：热电材料; 一个电场传感器; 第一导电电极，其包括与热电材料相邻的第一区域; 第二导电电极，其包括与所述电场传感器相邻的第二区域; 以及在第一导电电极和第二导电电极之间的导电互连，其中第一导电电极的第一区域大于第二导电电极的第二区域。

公开(公告)号：EP2960943A1

公开(公告)日：2015-12-30

申请号：EP15173323.5

申请日：2015-06-23

申请人： LG Display Co., Ltd.

发明人： HAN, Sang Kug ,  CHO, Ki Sul ,  PARK, Choon Ho ,  CHOI, Jin Ho ,  KIM, Kuk Hwan ,  KIM, Soo Hong ,  HAM, Eun Ji ,  SONG, Byoung Cheol

IPC分类号： H01L29/786

CPC分类号： H01L29/78696 ,  H01L29/0692 ,  H01L29/42384 ,  H01L29/78609 ,  H01L29/78645 ,  H01L29/78648

摘要： Disclosed is a thin film transistor (TFT) of a display apparatus which reduces a leakage current caused by a hump and thus decreases a screen defects. The TFT (100) includes an active layer (110) and a first gate electrode (120) disposed with a gate insulator (150) therebetween, and a source electrode (130) and a drain electrode (140) respectively disposed at both ends of the active layer (110). The gate electrode (120) branches as a plurality of lines and is disposed to overlap the active layer (110). The active layer (110) includes one or more channel areas (112) disposed between the source electrode (130) and the drain electrode (140), one or more dummy areas (114), and a plurality of link areas (116) disposed between the one or more channel areas (112) to connect the one or more channel areas (112) in one pattern. A length of each of the one or more dummy areas (114) extends from an edge of a corresponding channel area (112).

摘要翻译： 公开了一种显示装置的薄膜晶体管（TFT），其减少由隆起引起的漏电流，从而减少屏幕缺陷。 TFT（100）包括在其之间设置有栅绝缘体（150）的有源层（110）和第一栅电极（120），以及分别设置在栅极绝缘体（150）的两端的源电极（130）和漏电极 有源层（110）。 栅电极（120）以多条线分支，并配置成与有源层（110）重叠。 有源层（110）包括设置在源电极（130）和漏电极（140）之间的一个或多个沟道区（112），一个或多个虚拟区（114）和多个连接区（116） 在所述一个或多个通道区域（112）之间以一种图案连接所述一个或多个通道区域（112）。 一个或多个虚拟区域（114）中的每一个的长度从对应的通道区域（112）的边缘延伸。

公开(公告)号：EP2811527A3

公开(公告)日：2015-02-25

申请号：EP14153020.4

申请日：2014-01-29

申请人： MACRONIX INTERNATIONAL CO., LTD.

发明人： Lue, Hang-Ting ,  Chen, Wei-Chen

IPC分类号： H01L29/739 ,  H01L29/423

CPC分类号： H01L29/78645 ,  G11C16/0483 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26 ,  H01L27/092 ,  H01L27/11568 ,  H01L29/4232 ,  H01L29/66484 ,  H01L29/7391

摘要： A dual-mode transistor structure comprises a semiconductor body. The semiconductor body of the device includes a channel region, a p-type terminal region (operable as a source or drain) adjacent a first side of the channel region and an n-type terminal region (operable as a source or drain) adjacent a second side of the channel region. A gate insulator is disposed on a surface of the semiconductor body over the channel region. A gate is disposed on the gate insulator over the channel region. A first assist gate is disposed on a first side of the gate, and a second assist gate is disposed on a second side of the gate. Optionally, a back gate can be included beneath the channel region. Biasing the assist gates can be used to select n-channel or p-channel modes in a single device.

公开(公告)号：EP2500947A4

公开(公告)日：2013-09-04

申请号：EP09851281

申请日：2009-11-13

申请人： FUJITSU LTD

发明人： KONDO DAIYU ,  SATO SHINTARO

IPC分类号： H01L29/786 ,  H01L21/336 ,  H01L23/532 ,  H01L29/16 ,  H01L29/778

CPC分类号： H01L29/66045 ,  H01L21/02164 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/0228 ,  H01L21/02282 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02491 ,  H01L21/02502 ,  H01L21/02527 ,  H01L21/0262 ,  H01L21/02645 ,  H01L21/043 ,  H01L23/53276 ,  H01L29/1606 ,  H01L29/66015 ,  H01L29/66742 ,  H01L29/778 ,  H01L29/78645 ,  H01L29/78648 ,  H01L29/78684 ,  H01L29/78696 ,  H01L2924/0002 ,  Y10S977/734 ,  H01L2924/00

摘要： A semiconductor device including a graphene layer and a method of manufacturing the same are disclosed. A method in which graphene is grown on a catalyst metal by a chemical vapor deposition or the like is known. However, the graphene cannot be used as a channel, since the graphene is in contact with the catalyst metal, which is conductive. There is disclosed a method in which a catalyst film (2) is formed over a substrate (1), a graphene layer (3) is grown originating from the catalyst film (2), an electrode (4) in contact with the graphene layer (3) is formed, and the catalyst film (2) is removed.