公开(公告)号：EP2621253A1

公开(公告)日：2013-07-31

申请号：EP13152504.0

申请日：2013-01-24

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Muramatsu, Shigetsugu ,  Shimizu, Hiroshi ,  Kobayashi, Kazutaka

IPC: H05K3/20 ,  H05K3/00 ,  F21K99/00 ,  H05K1/02

CPC classification number: H01L33/60 ,  H01L25/0753 ,  H01L2224/13 ,  H01L2924/0002 ,  H05K1/0274 ,  H05K3/0014 ,  H05K3/0061 ,  H05K3/10 ,  H05K3/205 ,  H05K2201/0195 ,  H05K2201/0376 ,  H05K2201/09409 ,  H05K2201/10106 ,  H05K2201/2054 ,  Y10T29/49155 ,  H01L2924/00

Abstract: There is provided a wiring substrate (1). The wiring substrate includes: a heat sink (10); an insulating member (20, 30) on the heat sink; a wiring pattern (40) embedded in the insulating member and including a first surface (40A) and a second surface opposite to the first surface, the second surface contacting the insulating member; and a metal layer (50) on the first surface of the wiring pattern, wherein an exposed surface (50A) of the metal layer is flush with an exposed surface (30A) of the insulating member.

Abstract translation: 提供了布线基板（1）。 布线基板包括：散热片（10）; 绝热构件（20,30）; 嵌入绝缘构件中的布线图案（40），包括第一表面（40A）和与第一表面相对的第二表面，第二表面接触绝缘构件; 以及在所述布线图案的所述第一表面上的金属层（50），其中所述金属层的暴露表面（50A）与所述绝缘构件的暴露表面（30A）齐平。

公开(公告)号：EP2621250A1

公开(公告)日：2013-07-31

申请号：EP13152505.7

申请日：2013-01-24

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Muramatsu, Shigetsugu ,  Shimizu, Hiroshi ,  Horikawa, Yasuyoshi

IPC: H05K1/02 ,  H05K1/05 ,  F21K99/00 ,  H05K3/34

CPC classification number: H05K7/2039 ,  F21K9/90 ,  F21V7/00 ,  H01L2224/16225 ,  H05K1/0274 ,  H05K1/056 ,  H05K3/3452 ,  H05K3/46 ,  H05K2201/0191 ,  H05K2201/09409 ,  H05K2201/099 ,  H05K2201/10106 ,  H05K2201/2054

Abstract: There is provided a wiring substrate (1). The wiring substrate includes: a heat sink (10); an insulating layer (20) on the heat sink; first and second wiring patterns (30) on the insulating layer to be separated from each other at a certain interval; a first reflective layer (50) including a first opening (50X) on the insulating layer so as to cover the first and second wiring patterns, wherein a portion of the first and second wiring patterns is exposed from the first opening, and wherein the portion of the first and second wiring patterns is defined as a mounting region (CA) on which a light emitting element is to be mounted; and a second reflective layer (60) on the insulating layer, wherein the second reflective layer is interposed between the first and second wiring patterns. A thickness of the second reflective layer is smaller than that of the first reflective layer.

Abstract translation: 提供了一种布线基板（1）。 布线基板包括：散热器（10）; 散热器上的绝缘层（20） 在绝缘层上的第一和第二布线图案（30）以一定间隔彼此分开; 第一反射层（50），其在所述绝缘层上包括第一开口（50X）以覆盖所述第一布线图案和所述第二布线图案，其中所述第一布线图案和所述第二布线图案的一部分从所述第一开口暴露，并且其中， 第一布线图案和第二布线图案中的一个被定义为安装发光元件的安装区域（CA） 和在所述绝缘层上的第二反射层（60），其中所述第二反射层插入在所述第一和第二布线图案之间。 第二反射层的厚度小于第一反射层的厚度。

公开(公告)号：EP2190272A3

公开(公告)日：2012-01-18

申请号：EP09252645.8

申请日：2009-11-18

Applicant: Everlight Electronics Co., Ltd.

Inventor： Chao, Tzu-Hao

IPC: H05K3/32 ,  H05K1/11

CPC classification number: H05K1/181 ,  H01L23/49838 ,  H01L2924/0002 ,  H05K3/403 ,  H05K2201/09181 ,  H05K2201/09254 ,  H05K2201/09409 ,  H05K2201/10106 ,  Y02P70/611 ,  H01L2924/00

Abstract: A circuit structure (100) of a package carrier (S) including a plurality of chip pads (C), a first electrode (110), a second electrode (120), a third electrode (130) and a fourth electrode (140) are provided. These chip pads are arranged in an M×N array. A first bonding pad (P1), a second bonding pad (P2), a third bonding pad (P3) and a fourth bonding pad (P4) are disposed clockwise in the peripheral area of each chip pad in sequence. The orientations of each of the first, second, third, and fourth bonding pads of the (S-1) th row rotated by 90 degrees are equal to the orientations of each of the first, second, third and fourth bonding pads of the S th row, respectively. The first electrode is connected with each first bonding pad. The second electrode is connected with each second bonding pad. The third electrode is connected with each third bonding pad. The fourth electrode is connected with each fourth bonding pad.

公开(公告)号：EP2360661A1

公开(公告)日：2011-08-24

申请号：EP09827400.4

申请日：2009-07-01

Applicant: Sharp Kabushiki Kaisha

Inventor： MORIWAKI, Hiroyuki

IPC: G09F9/00 ,  G02F1/1345 ,  H01L21/768 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49

CPC classification number: H05K3/361 ,  H01L23/49811 ,  H01L27/0203 ,  H01L27/12 ,  H01L27/124 ,  H01L2924/0002 ,  H01L2924/14 ,  H05K1/025 ,  H05K1/113 ,  H05K3/323 ,  H05K2201/09227 ,  H05K2201/09409 ,  H05K2201/09436 ,  H05K2201/10128 ,  H01L2924/00

Abstract: Provided is a circuit substrate that affords a narrower frame in display devices or the like, while suppressing connection faults between wirings and external connection terminals. The invention is a circuit substrate having a substrate, on top of which wiring, an insulating film and an external connection terminal are disposed in order. The circuit substrate is provided with an anisotropic conductive film, having conductive particles, on the external connection terminal; and the external connection terminal is connected to the wiring via at least one contact hole formed in the insulating film, with the length from one end to the other end, in a plan view, of a region formed with one or more contact holes that connect to a specific external connection terminal being greater than the diameter of each of the conductive particles.

Abstract translation: 提供了一种在显示装置等中提供较窄帧的电路基板，同时抑制布线和外部连接端子之间的连接故障。 本发明是具有基板的电路基板，其上布置有布线，绝缘膜和外部连接端子。 电路基板在外部连接端子上设置有具有导电粒子的各向异性导电膜; 并且所述外部连接端子经由形成在所述绝缘膜中的至少一个接触孔连接到所述布线，所述接触孔的长度从一端到另一端在平面图中形成有形成有一个或多个接触孔的区域 到特定的外部连接端子大于每个导电颗粒的直径。

公开(公告)号：EP1873826A4

公开(公告)日：2010-08-25

申请号：EP06730385

申请日：2006-03-29

Applicant: MURATA MANUFACTURING CO

Inventor： SUESADA TSUYOSHI ,  HIGASHIBATA KAZUAKI ,  HOSOKAWA TOSHIHIRO ,  KAWATA MASAKI

IPC: H01L23/12 ,  H01L25/04 ,  H01L25/18

CPC classification number: H01L23/49816 ,  H01L23/15 ,  H01L23/49838 ,  H01L2224/16225 ,  H01L2224/81385 ,  H01L2924/09701 ,  H05K3/3442 ,  H05K2201/094 ,  H05K2201/09409 ,  H05K2201/10727 ,  Y02P70/613

公开(公告)号：EP2190272A2

公开(公告)日：2010-05-26

申请号：EP09252645.8

申请日：2009-11-18

Applicant: Everlight Electronics Co., Ltd.

Inventor： Chao, Tzu-Hao

IPC: H05K3/32 ,  H05K1/11

CPC classification number: H05K1/181 ,  H01L23/49838 ,  H01L2924/0002 ,  H05K3/403 ,  H05K2201/09181 ,  H05K2201/09254 ,  H05K2201/09409 ,  H05K2201/10106 ,  Y02P70/611 ,  H01L2924/00

Abstract: A circuit structure (100) of a package carrier (S) including a plurality of chip pads (C), a first electrode (110), a second electrode (120), a third electrode (130) and a fourth electrode (140) are provided. These chip pads are arranged in an M×N array. A first bonding pad (P1), a second bonding pad (P2), a third bonding pad (P3) and a fourth bonding pad (P4) are disposed clockwise in the peripheral area of each chip pad in sequence. The orientations of each of the first, second, third, and fourth bonding pads of the (S-1) th row rotated by 90 degrees are equal to the orientations of each of the first, second, third and fourth bonding pads of the S th row, respectively. The first electrode is connected with each first bonding pad. The second electrode is connected with each second bonding pad. The third electrode is connected with each third bonding pad. The fourth electrode is connected with each fourth bonding pad.

Abstract translation: 包括多个芯片焊盘（C），第一电极（110），第二电极（120），第三电极（130）和第四电极（140）的封装载体（S）的电路结构（100） 被提供。 这些芯片焊盘以M×N阵列排列。 第一接合焊盘（P1），第二接合焊盘（P2），第三接合焊盘（P3）和第四接合焊盘（P4）顺序地设置在每个芯片焊盘的周边区域中。 旋转90度的第（S-1）行的第一，第二，第三和第四接合焊盘中的每一个的取向等于S的第一，第二，第三和第四焊盘中的每一个的取向 行。 第一电极与每个第一接合焊盘连接。 第二电极与每个第二接合焊盘连接。 第三电极与每个第三接合焊盘连接。 第四电极与每个第四接合焊盘连接。

公开(公告)号：EP1992491A3

公开(公告)日：2009-04-29

申请号：EP08015764.7

申请日：2001-12-19

Applicant: Seiko Epson Corporation

Inventor： Ishizawa, Taku ,  Fukano, Takakazu ,  Saruta, Toshihisa

IPC: B41J2/175

CPC classification number: B41J2/17546 ,  B41J2/17503 ,  B41J2/17526 ,  B41J2/1753 ,  H05K1/117 ,  H05K2201/09409 ,  H05K2201/09709 ,  H05K2201/10159

Abstract: A circuit board (10) mounted on a marking material receptacle and having a storage device for storing data relating to a marking material for print, said circuit board (10) comprising a plurality of terminals (21-27) arranged on said circuit board (10) in a single direction and connected to the storage device, wherein two of said plurality of terminals (21-27) arranged at two edges of the circuit board (10) are ground terminals (24, 27) used for determining if the marking material receptacle has been installed correctly, wherein one of said ground terminals (24, 27) receives ground potential from a printer when the marking material receptacle is installed on the printer, and another of said ground terminals (24, 27) is connected to the one of said ground terminals (24, 27) on the circuit board (10) and to be connected to a cartridge out detecting pin of the printer when the marking material receptacle is installed on the printer.

公开(公告)号：EP1450405A3

公开(公告)日：2007-08-29

申请号：EP04002985.2

申请日：2004-02-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hwang, Seong-Yong ,  Kang, Sung-Chul ,  Oh, Weon-Sik ,  Jeong, Cheol-Yong ,  Lee, Jin-Suk ,  Yoon, Ju-Young ,  Cho, Won-gu

IPC: G02F1/13 ,  H01L21/60 ,  H01L23/538 ,  H01L23/498

CPC classification number: G02F1/13452 ,  G02F2001/13456 ,  H01L23/49838 ,  H01L24/17 ,  H01L24/29 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/13016 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/29101 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/81801 ,  H01L2224/81903 ,  H01L2224/83192 ,  H01L2224/838 ,  H01L2224/83851 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0781 ,  H01L2924/14 ,  H05K1/111 ,  H05K3/323 ,  H05K2201/0367 ,  H05K2201/09409 ,  H05K2201/09709 ,  H05K2201/10674 ,  H01L2924/00 ,  H01L2224/0401

Abstract: In a drive IC and a display device having the same, the drive IC includes a plurality of bumps disposed on a lower surface of the drive IC and aligned in a plurality of rows along an edge of the drive IC. The bumps aligned in different rows from each other are juxtaposed in a direction perpendicular to a direction in which the bumps are aligned. Accordingly, when the drive IC is mounted on a display panel using an anisotropic conductive film, the anisotropic conductive film may be smoothly flowed through a space defined by the bumps of the drive IC, thereby improving electric properties of the drive IC and display device.

公开(公告)号：EP1598198A3

公开(公告)日：2006-05-24

申请号：EP05018578.4

申请日：2001-12-19

Applicant: SEIKO EPSON CORPORATION

Inventor： Ishizawa, Taku ,  Fukano, Takakazu ,  Saruta, Toshihisa

IPC: B41J2/175

CPC classification number: B41J2/17546 ,  B41J2/17503 ,  B41J2/17526 ,  B41J2/1753 ,  H05K1/117 ,  H05K2201/09409 ,  H05K2201/09709 ,  H05K2201/10159

Abstract: A circuit board (10; 200) for a marking material receptacle (40, 48), comprising a storage device (30) for storing data relating to a marking material for print, a plurality of terminals (21-27; 201-207) arranged on said circuit board (10; 200), said terminals comprising a power supply terminal (22; 202) and being arranged in a plurality of rows, characterized by two ground terminals (24, 27; 204, 207) arranged for allowing a printing device (100) to determine if said marking material receptacle has been installed correctly, where said ground terminals (24, 27; 204, 207) are located at the outermost ends of a row that is different than the row that contains said power supply terminal (22; 202), and where said ground terminals (24, 27; 202, 204) are not the terminals in closest proximity to said power supply terminal (22; 202).

Abstract translation: 电路板（10）具有基本为矩形的形状，设置在并置面（13）的上半部具有大致圆形的测试端子（20）。 在下半部设置有多个基本上矩形的端子（21-27），其排列成两行，即上下排，上排包含用于数据输入/输出的I / O端子（21）， 用于供电的电源端子（22）和用于输入芯片选择信号CS的芯片选择端子（23）。 并排面（13）的下排包含接地端子（24），用于输入读/写控制信号W / R的读/写端子（25），用于输入时钟信号CLK的时钟端子（26） 接地端子（27）。

公开(公告)号：EP0389826A1

公开(公告)日：1990-10-03

申请号：EP90104127.7

申请日：1990-03-02

Applicant: SEIKO EPSON CORPORATION

Inventor： Sato, Eiichi, c/o Seiko Epson Corporation

IPC: H05K13/00 ,  H01L21/00

CPC classification number: H01L21/67144 ,  H01L21/56 ,  H01L21/67126 ,  H01L23/3121 ,  H01L24/97 ,  H01L2224/50 ,  H01L2224/97 ,  H05K1/181 ,  H05K3/284 ,  H05K2201/09072 ,  H05K2201/09409 ,  H05K2201/09709 ,  H05K2201/10522 ,  H05K2201/10545 ,  H05K2201/10681 ,  H05K2203/1316 ,  H05K2203/1572 ,  Y02P70/611 ,  H01L2224/86

Abstract: Semiconductor devices are each arranged such that a semiconductor chip (6) is disposed on a film carrier (1), fingers (3) of the film carrier are respectively connected to a multiplicity of electrodes provided on the semiconductor chip, and the fingers are then trimmed, or the fingers are trimmed after the semiconductor chip and parts of the fingers are sealed with a resin (12) or the like. The semiconductor devices thus arranged are respectively mounted on both obverse and reverse surfaces of a substrate at mutually opposing positions thereof, the substrate having electrically conductive patterns (21) formed on the both surfaces thereof. The semiconductor devices are sealed with a resin or the like so as to be formed integrally with the substrate.

Abstract translation: 半导体器件分别设置搜索做了半导体芯片（6）被设置在膜载体（1）上，手指（3）分别连接到电极的多个设置于半导体芯片上的膜载体，和手指然后 修整，或手指的半导体芯片后修整和手指部分用的树脂（12）或类似物密封。 半导体器件分别安装如此布置在两个正面和反面在相互相对的位置上，具有形成在两个其表面上的导电图案（21）在基板一个基板的表面上。 半导体器件被密封用树脂或类似物，以便被与基片一体地形成。