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675 条记录 (耗时 0.015 秒)

    MISFET
    112.
    发明公开
    MISFET 有权

    公开(公告)号：EP1286398A4

    公开(公告)日：2003-02-26

    申请号：EP00976351

    申请日：2000-11-20

    申请人： MATSUSHITA ELECTRIC IND CO LTD

    发明人： YOKOGAWA TOSHIYA ,  KITABATAKE MAKOTO ,  KUSUMOTO OSAMU ,  TAKAHASHI KUNIMASA ,  UENOYAMA TAKESHI

    IPC分类号： H01L21/04 ,  H01L29/10 ,  H01L29/24 ,  H01L29/36 ,  H01L29/772 ,  H01L29/78 ,  H01L29/06 ,  H01L29/778

    CPC分类号： H01L29/7813 ,  H01L21/0455 ,  H01L29/105 ,  H01L29/1608 ,  H01L29/365 ,  H01L29/66068 ,  H01L29/7725 ,  H01L29/78 ,  H01L29/7828 ,  H01L29/7838

    摘要： P-type active region 12; n-type source/drain regions 13a and 13b; gate insulating film 14 made of a thermal oxide film; gate electrode 15; source/drain electrodes 16a and 16b, are provided over a p-type SiC substrate 11. In the active region 12, p-type heavily doped layers 12a, which are thin enough to create a quantum effect, and thick undoped layers 12b are alternately stacked. When carriers flow, scattering of impurity ions in the active region is reduced, and the channel mobility increases. In the OFF state, a depletion layer expands throughout the active region, and the breakdown voltage increases. As a result of reduction in charges trapped in the gate insulating film or near the interface between the gate insulating film and the active region, the channel mobility further increases.

    摘要翻译： MISFET包括其上设置有p型有源区（12），n型源极区和漏极区（13a，13b），由热氧化物组成的栅极氧化物（14）的p型SiC衬底（11） 栅电极（15），源电极（16a）和漏电极（16b）。 有源区（12）包括足够薄以允许量子效应的重掺杂p型层（12a）和未掺杂厚层（12b）的叠层。 载流子迁移率随着移动载流子存在下有源区中杂质离子的散射减少而增加，而由于截止状态下整个有源区中的耗尽导致击穿强度增加。 沟道迁移率进一步增加，因为较少的电荷被俘获在栅极氧化物中以及栅极氧化物与有源区之间的界面附近。

    Electrode for silicon carbide semiconductor, silicon carbide semiconductor element comprising the electrode, and production method therefor
    114.
    发明公开
    Electrode for silicon carbide semiconductor, silicon carbide semiconductor element comprising the electrode, and production method therefor 有权
    Verfahren zur Herstellung einer ElektrodefürSiliziumkarbidhalbleiter

    公开(公告)号：EP1246252A2

    公开(公告)日：2002-10-02

    申请号：EP02252154.6

    申请日：2002-03-26

    申请人： NGK SPARK PLUG CO., LTD

    发明人： Nakashima, Kenshiro ,  Okuyama, c/o NGK Spark Plug Co Ltd ,  Yokoi, Hitoshi, c/o NGK Spark Plug Co. Ltd ,  Oshima, Takafumi, c/o NGK Spark Plug Co Ltd

    IPC分类号： H01L29/45 ,  H01L29/24 ,  H01L21/28

    CPC分类号： H01L21/0485 ,  H01L29/1608 ,  H01L29/45

    摘要： An ohmic electrode for an SiC semiconductor includes a p-type Si layer formed on the surface of a p-type SiC semiconductor, and a metal silicide layer formed on the surface of the Si layer, the metal silicide layer being formed from a metal silicide such as PtSi. The p-type Si layer is preferably formed from p-type Si having a carrier concentration equal to or higher than that of the aforementioned p-type SiC. Preferably, the ohmic electrode is formed as follows: deposition of Si is performed; deposition of a metal silicide is performed by means of laser ablation; laser irradiation is performed to thereby improve ohmic properties and enhance adhesion between the resultant deposition layer and the p-type SiC semiconductor; and then further deposition of the metal silicide is performed by means of laser ablation.

    摘要翻译： 用于SiC半导体的欧姆电极包括在p型SiC半导体的表面上形成的p型Si层和在Si层的表面上形成的金属硅化物层，金属硅化物层由金属硅化物形成 如PtSi。 p型Si层优选由具有等于或高于上述p型SiC的载流子浓度的p型Si形成。 优选地，欧姆电极形成如下：进行Si的沉积; 通过激光烧蚀进行金属硅化物的沉积; 进行激光照射，从而提高欧姆性能，增强所得到的沉积层和p型SiC半导体之间的粘附性; 然后通过激光烧蚀进行金属硅化物的进一步沉积。

    Field effect transistor and method of manufacturing the same
    117.
    发明公开
    Field effect transistor and method of manufacturing the same 审中-公开
    场效应晶体管及其制造方法

    公开(公告)号：EP1143526A2

    公开(公告)日：2001-10-10

    申请号：EP01303280.0

    申请日：2001-04-06

    申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.

    发明人： Kitabatake, Makoto ,  Uchida, Masao ,  Yokogawa, Toshiya ,  Takahashi, Kunimasa ,  Kusumoto, Osamu

    IPC分类号： H01L29/78 ,  H01L29/24 ,  H01L29/20 ,  H01L21/04 ,  H01L21/336

    CPC分类号： H01L29/0634 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/20 ,  H01L29/66068 ,  H01L29/66712 ,  H01L29/7802 ,  H01L29/7813

    摘要： There are provided a field effect transistor with a high withstand voltage and low loss and a method of manufacturing the same. The field effect transistor includes an n-type substrate 11, an n-type semiconductor layer 12 formed on the n-type substrate 11, a p-type semiconductor layer 13 formed on the n-type semiconductor layer 12, a p-type region 14 embedded in the n-type semiconductor layer 12, an n-type region 15 embedded in the n-type semiconductor layer 12 and the p-type semiconductor layer 13, an n-type source region 16 disposed in the p-type semiconductor layer 13 on its surface side, an insulating layer 17 disposed on the p-type semiconductor layer 13, a gate electrode 18 disposed on the insulating layer 17, a source electrode 19, and a drain electrode 20. The n-type semiconductor layer 12, the p-type semiconductor layer 13, and the p-type region 14 are made of wide-gap semiconductors with a bandgap of at least 2eV, respectively.

    摘要翻译： 提供了一种具有高耐压和低损耗的场效应晶体管及其制造方法。 场效应晶体管包括：n型衬底11，形成在n型衬底11上的n型半导体层12，形成在n型半导体层12上的p型半导体层13，形成在p型半导体层12上的p型区域 埋入n型半导体层12中的n型区15，埋入n型半导体层12和p型半导体层13中的n型区15，设置在p型半导体层12中的n型源极区16 13，在其表面侧配置的绝缘层17，配置在p型半导体层13上的绝缘层17，配置在绝缘层17上的栅极电极18，源极电极19和漏极电极20.n型半导体层12， p型半导体层13以及p型区域14分别由带隙为2eV以上的宽带隙半导体构成。

    ELEVATED CHANNEL MOSFET
    118.
    发明公开
    ELEVATED CHANNEL MOSFET 审中-公开
    增加沟道MOSFET

    公开(公告)号：EP1121716A2

    公开(公告)日：2001-08-08

    申请号：EP99969844.2

    申请日：1999-08-26

    申请人： Conexant Systems, Inc.

    发明人： AUGUSTO, Carlos

    IPC分类号： H01L21/336 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/10 ,  H01L29/24 ,  H01L29/49 ,  H01L29/51 ,  H01L21/28 ,  H01L27/092

    CPC分类号： H01L21/28194 ,  H01L21/28017 ,  H01L21/28088 ,  H01L21/28167 ,  H01L21/76895 ,  H01L21/823878 ,  H01L27/0928 ,  H01L29/1054 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66477 ,  H01L29/66537 ,  H01L29/66545 ,  H01L29/66651

    摘要： The present invention provides a method of producing a semiconductor device (e.g., a Metal Oxide Semiconductor Field Effect Transistor (MOSFET)) with a gate length less than 0.25 microns using standard process techniques arranged in an unstandardized process order. The process flow of the present invention provides for the implantation and thermal processing of the wells and junctions prior to the growth of a channel or the deposition of the gate stack. By implanting and annealing the wells and junctions prior to the formation of the channel and gate, the present invention allows a greater variety of materials to be utilized as the channel and gate materials than are available under process flows currently known; undoped materials may be used to form the channel, metal oxides and similar materials with large dielectrics may be used to form a gate stack, and barrier metals and pure metals (copper, tungsten, etc.) may be used as gate electrodes. The present invention also provides for the selective epitaxial growth of a channel material elevated above the surface of a wafer containing a well and junctions. By providing an elevated channel, higher mobility may be achieved; thereby enabling a higher current flow at a lower voltage through a semiconductor device.