公开(公告)号：EP1265295A3

公开(公告)日：2004-05-12

申请号：EP02012326.1

申请日：2002-06-04

申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.

发明人： Uchida, Masao ,  Kitabatake, Makoto ,  Yokogawa, Toshiya ,  Kusumoto, Osamu ,  Takahashi, Kunimasa ,  Miyanaga, Ryoko ,  Yamashita, Kenya

IPC分类号： H01L29/872 ,  H01L29/24 ,  H01L29/47 ,  H01L21/329 ,  H01L21/04 ,  H01L21/338

CPC分类号： H01L29/66143 ,  H01L29/1608 ,  H01L29/872

摘要： A Schottky diode (10) includes a semiconductor substrate (11) made of 4H-SiC, an epitaxially grown 4H-SiC layer (12), an ion implantation layer (13), a Schottky electrode (14), an ohmic electrode (15), and an insulative layer (16) made of a thermal oxide film. The Schottky electrode (14) and the insulative layer (16) are not in contact with each other, with a gap (17) being provided therebetween, whereby an altered layer does not occur. Therefore, it is possible to suppress the occurrence of a leak current.

摘要翻译： 肖特基二极管（10）包括由4H-SiC制成的半导体衬底（11），外延生长的4H-SiC层（12），离子注入层（13），肖特基电极（14），欧姆电极（15） ）和由热氧化膜制成的绝缘层（16）。 肖特基电极（14）和绝缘层（16）彼此不接触，在它们之间设置有间隙（17），由此不发生改变的层。 因此，可以抑制泄漏电流的发生。

公开(公告)号：EP0952645A3

公开(公告)日：2001-03-21

申请号：EP99107985.6

申请日：1999-04-22

申请人： Matsushita Electric Industrial Co., Ltd.

发明人： Kamiyama, Satoshi ,  Kume, Masahiro ,  Miyanaga, Ryoko ,  Kidoguchi, Isao ,  Ban, Yuzaburo ,  Tsujimura, Ayumu ,  Hasegawa, Yoshiaki ,  Ishibashi, Akihiko

IPC分类号： H01S3/19

CPC分类号： B82Y20/00 ,  H01S5/3054 ,  H01S5/3063 ,  H01S5/343 ,  H01S5/34333

摘要： A GaN buffer layer (12) and an Si-doped n-type GaN contact layer (13) are formed in this order on a sapphire substrate (11). An n-type Al 0.3 Ga 0.7 N cladding layer (14), an n-type Al 0.25 Ga 0.75 N optical guide layer (15), a multi-quantum well active layer (16), in which Al 0.2 Ga 0.8 N well layers and Al 0.25 Ga 0.75 N barrier layers are alternately stacked, an Mg-doped p-type Al 0.25 Ga 0.75 N optical guide layer (17), a p-type Al 0.4 Ga 0.6 N 0.98 P 0.02 cladding layer (18) and a p-type GaN contact layer (19) are stacked in this order on an active region on the upper surface of the n-type contact layer.

公开(公告)号：EP0911887A2

公开(公告)日：1999-04-28

申请号：EP98120254.2

申请日：1998-10-26

申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.

发明人： Kamiyama, Satoshi ,  Yoshii, Shigeo ,  Miyanaga, Ryoko ,  Nishikawa, Takashi ,  Saitoh, Tohru ,  Sasai, Yoichi

IPC分类号： H01L33/00

CPC分类号： H01L33/40 ,  H01L33/145 ,  H01L33/38 ,  H01L33/42

摘要： The light-emitting diode device of the present invention includes an active layer (17), a p-type contact layer (22), a Schottky electrode (23) and an ohmic electrode (24). The active layer is formed over an n-type semiconductor substrate (11). The contact layer (22) is formed over the active layer (17). The Schottky electrode (23) is selectively formed on a portion of the contact layer (22) and makes Schottky contact with said portion of the contact layer (22). The ohmic electrode (24) surrounds the Schottky electrode (23) on the contact layer (22), is electrically connected to the Schottky electrode (23), and transmits the light emitted from the active layer (17). Alternatively, the Schottky electrode may be replaced by a pad electrode (42A) in ohmic contact with the contact layer (22,41A), a high-resistance region (43) being formed as a current blocking layer under the pad electrode (42A).

摘要翻译： 本发明的发光二极管器件包括有源层（17），p型接触层（22），肖特基电极（23）和欧姆电极（24）。 有源层形成在n型半导体衬底（11）上。 接触层（22）形成在有源层（17）上。 肖特基电极（23）选择性地形成在接触层（22）的一部分上，并与接触层（22）的所述部分进行肖特基接触。 欧姆电极（24）围绕接触层（22）上的肖特基电极（23），电连接到肖特基电极（23），并透射从有源层（17）发射的光。 或者，肖特基电极可以由与接触层（22,41A）欧姆接触的焊盘电极（42A）替代，高电阻区域（43）形成为焊盘电极（42A）下方的电流阻挡层， 。

公开(公告)号：EP1968104A3

公开(公告)日：2008-11-05

申请号：EP08011174.3

申请日：2003-07-09

申请人： Matsushita Electric Industrial Co., Ltd.

发明人： Kusumoto, Osamu ,  Kitabatake, Makoto ,  Takahashi, Kunimasa ,  Yamashita, Kenya c/o Matsushita Electric Industrial Co., Ltd ,  Miyanaga, Ryoko ,  Uchida, Masao

IPC分类号： H01L21/28 ,  H01L29/78 ,  H01L21/336 ,  H01L21/82 ,  H01L29/872 ,  H01L29/812 ,  H01L29/45 ,  H01L27/06 ,  H01L29/772

CPC分类号： H01L29/7813 ,  H01L21/0485 ,  H01L21/8213 ,  H01L27/0605 ,  H01L27/0629 ,  H01L29/1029 ,  H01L29/105 ,  H01L29/1608 ,  H01L29/365 ,  H01L29/41766 ,  H01L29/66068 ,  H01L29/7725 ,  H01L29/7828 ,  H01L29/7838 ,  H01L29/812 ,  H01L29/872 ,  Y10S438/931

摘要： An accumulation-mode MISFET comprises: a high-resistance SiC layer 102 epitaxially grown on a SiC substrate 101; a well region 103; an accumulation channel layer 104 having a multiple δ-doped layer formed on the surface region of the well region 103; a contact region 105; a gate insulating film 108; and a gate electrode 110. The accumulation channel layer 104 has a structure in which undoped layers 104b and δ-doped layers 104a allowing spreading movement of carriers to the undoped layers 104b under a quantum effect are alternately stacked. A source electrode 111 is provided which enters into the accumulation channel layer 104 and the contact region 105 to come into direct contact with the contact region 105. It becomes unnecessary that a source region is formed by ion implantation, leading to reduction in fabrication cost.

摘要翻译： 累积模式MISFET包括：在SiC衬底101上外延生长的高电阻SiC层102; 井区域103; 具有在阱区103的表面区域上形成的多个δ掺杂层的累积沟道层104; 接触区域105; 栅极绝缘膜108; 和栅极电极110.积聚沟道层104具有这样的结构，其中交替堆叠允许载流子在量子效应下扩散到未掺杂层104b的运动的未掺杂层104b和δ掺杂层104a。 提供源电极111，其进入到积累沟道层104和接触区域105中以与接触区域105直接接触。不需要通过离子注入形成源区域，从而导致制造成本的降低。

公开(公告)号：EP1220304A3

公开(公告)日：2008-10-08

申请号：EP01130923.4

申请日：2001-12-27

申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.

发明人： Ishibashi, Akihiko ,  Tsujimura, Ayumu ,  Hasegawa, Yoshiaki ,  Otsuka, Nobuyuki ,  Sugahara, Gaku ,  Miyanaga, Ryoko ,  Shimamoto, Toshitaka ,  Harafuji, Kenji ,  Ban, Yuzaburoji ,  Ohnaka, Kiyoshi

IPC分类号： H01L21/20 ,  H01L33/00

CPC分类号： H01L33/007 ,  B82Y20/00 ,  H01L21/0242 ,  H01L21/02458 ,  H01L21/02507 ,  H01L21/0254 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/0265 ,  H01L33/32 ,  H01S5/22 ,  H01S5/3063 ,  H01S5/3215 ,  H01S5/3216 ,  H01S5/34333 ,  H01S2304/04 ,  H01S2304/12

摘要： The method for fabricating a nitride semiconductor of the present invention includes the steps of: (1) growing a first semiconductor layer made of a first group III nitride over a substrate by supplying a first group III source and a group V source containing nitrogen; and (2) growing a second semiconductor layer made of a second group III nitride on the first semiconductor layer by supplying a second group III source and a group V source containing nitrogen. At least one of the steps (1) and (2) includes the step of supplying a p-type dopant over the substrate, and an area near the interface between the first semiconductor layer and the second semiconductor layer is grown so that the density of the p-type dopant locally increases.

公开(公告)号：EP1523032A3

公开(公告)日：2007-09-26

申请号：EP04023713.3

申请日：2004-10-05

申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD

发明人： Yamashita, Kenya ,  Kitabatake, Makoto ,  Kusumoto, Osamu ,  Takahashi, Kunimasa ,  Uchida, Masao ,  Miyanaga, Ryoko

IPC分类号： H01L21/04

CPC分类号： H01L29/518 ,  H01L21/049 ,  H01L29/1608 ,  H01L29/41766 ,  H01L29/513 ,  H01L29/66068 ,  H01L29/7827 ,  H01L29/7828

摘要： A gate insulating film which is an oxide layer mainly made of SiO 2 is formed over a silicon carbide substrate by thermal oxidation, and then, a resultant structure is annealed in an inert gas atmosphere in a chamber. Thereafter, the silicon carbide-oxide layered structure is placed in a chamber which has a vacuum pump and exposed to a reduced pressure NO gas atmosphere at a high temperature higher than 1100°C and lower than 1250°C, whereby nitrogen is diffused in the gate insulating film. As a result, a gate insulating film which is a V-group element containing oxide layer, the lower part of which includes a high nitrogen concentration region, and the relative dielectric constant of which is 3.0 or higher, is obtained. The interface state density of an interface region between the V-group element containing oxide layer and the silicon carbide layer decreases.

公开(公告)号：EP1306890A2

公开(公告)日：2003-05-02

申请号：EP02023730.1

申请日：2002-10-23

申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.

发明人： Takahashi, Kunimasa ,  Uchida, Masao ,  Kitabatake, Makoto ,  Yokogawa, Toshiya ,  Kusumoto, Osamu ,  Yamashita, Kenya ,  Miyanaga, Ryoko

IPC分类号： H01L21/04

CPC分类号： H01L29/365 ,  C30B25/02 ,  C30B29/36 ,  H01L21/02378 ,  H01L21/02433 ,  H01L21/02529 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/02584 ,  H01L21/0262 ,  H01L21/02661 ,  H01L21/0445 ,  H01L29/0657 ,  H01L29/1608 ,  H01L29/66068

摘要： A SiC bulk substrate whose top face has been flattened is placed in a vertical thin film growth system to be annealed in an inert gas atmosphere. A material gas of Si is then supplied at a flow rate of 1 mL/min. at a substrate temperature of 1200°C through 1600°C. Subsequently, the diluent gas is changed to a hydrogen gas at a temperature of 1600°C, and material gases of Si and carbon are supplied with nitrogen intermittently supplied, so as to deposit SiC thin films on the SiC bulk substrate. In a flat δ -doped multilayered structure thus formed, an average height of macro steps formed on the top face and on interfaces therein is 30 nm or less. When the resultant substrate is used, a semiconductor device with a high breakdown voltage and high mobility can be realized.

摘要翻译： 将其顶面平坦化的SiC体基板放置在垂直薄膜生长系统中，以在惰性气体气氛中进行退火。 然后以1mL / min的流速供给Si的原料气体。 在1200℃〜1600℃的基板温度下，在1600℃的温度下将稀释气体变为氢气，向间歇地供给氮气的Si和碳的原料气体供给，以沉积 在SiC体基板上的SiC薄膜。 在如此形成的平坦的三角形多层结构的结构中，形成在顶面上和其界面上的宏步骤的平均高度为30nm或更小。 当使用所得到的衬底时，可以实现具有高击穿电压和高迁移率的半导体器件。

公开(公告)号：EP1104031A2

公开(公告)日：2001-05-30

申请号：EP00124829.3

申请日：2000-11-14

申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.

发明人： Kidoguchi, Isao ,  Ishibashi, Akihiko ,  Miyanaga, Ryoko ,  Sugahara, Gaku ,  Suzuki, Masakatsu ,  Kume, Masahiro ,  Ban, Yuzaburo ,  Morita, Kiyoyuki ,  Tsujimura, Ayumu ,  Hasegawa, Yoshiaki

IPC分类号： H01L33/00 ,  H01L21/20

CPC分类号： H01L33/12 ,  H01L21/0237 ,  H01L21/0242 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02639 ,  H01L21/02642 ,  H01L21/0265 ,  H01L33/007 ,  H01L33/405 ,  H01L33/46 ,  H01S5/2077 ,  H01S5/2201 ,  H01S5/32341 ,  H01S5/4031 ,  H01S2304/00

摘要： The method of fabricating a nitride semiconductor of this invention includes the steps of forming, on a substrate, a first nitride semiconductor layer of Al u Ga v In w N, wherein 0 ≦ u, v, w ≦ 1 and u + v + w = 1; forming, in an upper portion of the first nitride semiconductor layer, plural convexes extending at intervals along a substrate surface direction; forming a mask film for covering bottoms of recesses formed between the convexes adjacent to each other; and growing, on the first nitride semiconductor layer, a second nitride semiconductor layer of Al x Ga y In z N, wherein 0 ≦ x, y, z ≦ 1 and x + y + z = 1, by using, as a seed crystal, C planes corresponding to top faces of the convexes exposed from the mask film.

摘要翻译： 制造本发明的氮化物半导体的方法包括以下步骤：在衬底上形成AluGavInwN的第一氮化物半导体层，其中0≤v，w 1，u + v + w =​​ 1 ; 在所述第一氮化物半导体层的上部形成沿着基板表面方向间隔地延伸的多个凸部; 形成用于覆盖形成在彼此相邻的凸起之间的凹部的底部的掩模膜; 并且在第一氮化物半导体层上生长Al x Ga y In z N的第二氮化物半导体层，其中0≤x，y，z 1，x + y + z = 1，通过使用晶种C 对应于从掩模膜暴露的凸起的顶面的平面。

公开(公告)号：EP0952645A2

公开(公告)日：1999-10-27

申请号：EP99107985.6

申请日：1999-04-22

申请人： Matsushita Electric Industrial Co., Ltd.

发明人： Kamiyama, Satoshi ,  Kume, Masahiro ,  Miyanaga, Ryoko ,  Kidoguchi, Isao ,  Ban, Yuzaburo ,  Tsujimura, Ayumu ,  Hasegawa, Yoshiaki ,  Ishibashi, Akihiko

IPC分类号： H01S3/19

CPC分类号： B82Y20/00 ,  H01S5/3054 ,  H01S5/3063 ,  H01S5/343 ,  H01S5/34333

摘要： A GaN buffer layer (12) and an Si-doped n-type GaN contact layer (13) are formed in this order on a sapphire substrate (11). An n-type Al 0.3 Ga 0.7 N cladding layer (14), an n-type Al 0.25 Ga 0.75 N optical guide layer (15), a multi-quantum well active layer (16), in which Al 0.2 Ga 0.8 N well layers and Al 0.25 Ga 0.75 N barrier layers are alternately stacked, an Mg-doped p-type Al 0.25 Ga 0.75 N optical guide layer (17), a p-type Al 0.4 Ga 0.6 N 0.98 P 0.02 cladding layer (18) and a p-type GaN contact layer (19) are stacked in this order on an active region on the upper surface of the n-type contact layer.

摘要翻译： 在蓝宝石衬底（11）上依次形成GaN缓冲层（12）和Si掺杂的n型GaN接触层（13）。 一种n型Al0.3Ga0.7N包层（14），n型Al0.25Ga0.75N光导层（15），多量子阱有源层（16），其中Al0.2Ga0.8N阱 Mg掺杂的p型Al 0.25 Ga 0.75 N光导层17，p型Al 0.4 Ga 0.6 N 0.98 P 0.02包层（18）和Al 0.25 Ga 0.75 N阻挡层交替堆叠， 和p型GaN接触层（19）以此顺序堆叠在n型接触层的上表面上的有源区上。