公开(公告)号：EP0616335A2

公开(公告)日：1994-09-21

申请号：EP94101897.0

申请日：1994-02-08

Applicant: FUJITSU LIMITED

Inventor： Kumakura, Sinsuke, c/o Fujitsu Limited ,  Yamazaki, Hirokazu, c/o Fujitsu Limited ,  Watanabe, Hisayoshi, c/o Fujitsu Limited ,  Kasa, Yasushi, c/o Fujitsu Limited

IPC: G11C29/00 ,  G11C16/06

CPC classification number: G11C29/021 ,  G11C5/14 ,  G11C5/143 ,  G11C7/062 ,  G11C16/04 ,  G11C29/02 ,  G11C29/24 ,  G11C29/44 ,  G11C29/50 ,  G11C29/50004 ,  G11C29/50016 ,  G11C2029/5006

Abstract: An object of the present invention is to provide a semiconductor device that permits easy and efficient testing. A nonvolatile semiconductor memory comprises word lines WLi and bit lines BLi, a memory cell matrix 17 consisting of nonvolatile memory cells Cij, a sense amplifier 15, a write/erase timing circuit 9 for performing timing control necessary for write and erase operations, and a status register 2 for storing the operating state of the memory at the completion of the operation of the circuit 9, wherein there are provided, outside the address of the memory cell matrix 17, two kinds of dummy cells, D1, D2, D3,..., whose values are fixed to different values that induce different outputs from the sense amplifier 15. A pass condition or a fail condition is generated by accessing the dummy cells.

Abstract translation: 本发明的一个目的是提供一种允许容易和有效测试的半导体器件。 非易失性半导体存储器包括字线WLi和位线BLi，由非易失性存储单元Cij组成的存储单元矩阵17，读出放大器15，用于执行写和擦除操作所需的定时控制的写/擦除定时电路9，以及 状态寄存器2，用于在电路9的操作完成时存储存储器的工作状态，其中在存储单元矩阵17的地址外提供两种虚拟单元D1，D2，D3。 它们的值被固定到从感测放大器15引起不同输出的不同值。通过访问虚拟单元来产生通过条件或失败条件。

公开(公告)号：EP0543408A2

公开(公告)日：1993-05-26

申请号：EP92119825.5

申请日：1992-11-20

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Kushiyama, Natsuki, c/o Intellectual Property Div. ,  Furuyama, Tohru, c/o Intellectual Property Div. ,  Numata, Kenji, c/o Intellectual Property Div.

IPC: G11C29/00

CPC classification number: G11C29/025 ,  G11C11/401 ,  G11C29/02 ,  G11C29/028 ,  G11C29/24 ,  G11C29/50 ,  G11C2029/5004 ,  G11C2029/5006

Abstract: A semiconductor memory comprises a dynamic type memory cell array (10) arranged to form a matrix and provided with word lines (WL1 to WLm) commonly connected to memory cells (MC) of respective columns and bit lines (BLl through BLn) commonly connected to memory cells of respective rows, a dummy cell section (11) having a first set of dummy word lines (DWL) connected to respective complimentary bit line pairs (BL, /BL) of said memory cell array by way of respective first capacitances (C) and a second set of dummy word lines (/DWL) connected to respective complementary bit line pairs of said memory cell array by way of respective second capacitances (C), a dummy word line potential control circuit (15) capable of optionally controlling the mode of driving selected dummy word lines when said word lines of said memory cell array are activated and sense amplifiers (SAl to SAn) connected to the respective complementary bit line pairs of said memory cell array for reading data from selected memory cells of the memory cell array onto the related bit line.

Abstract translation: 半导体存储器包括布置成形成矩阵并且具有公共连接到各列的存储单元（MC）的字线（WL1至WLm）的动态型存储单元阵列（10），位线（BL1至BLn）共同连接到 各个行的存储单元，具有通过相应的第一电容（C）连接到所述存储单元阵列的相应的互补位线对（BL，/ BL）的第一组虚拟字线（DWL）的虚拟单元部分（11） ）和通过相应的第二电容（C）连接到所述存储单元阵列的相应互补位线对的第二组虚拟字线（/ DWL），一个虚拟字线电位控制电路（15），能够可选地控制 当所述存储单元阵列的所述字线被激活时驱动所选虚拟字线的模式，以及连接到所述存储单元阵列的相应互补位线对的读出放大器（SA1至SAn），用于从选择的m读取数据 存储单元阵列的emory单元到相关位线上。

公开(公告)号：EP0462876B1

公开(公告)日：1992-12-30

申请号：EP91401591.2

申请日：1991-06-14

Applicant: SGS-THOMSON MICROELECTRONICS S.A.

Inventor： Conan, Bertrand, Cabinet BALLOT-SCHMIT

IPC: G11C29/00

CPC classification number: G11C29/50 ,  G11C16/04 ,  G11C2029/5006

Abstract: In order to reduce the number of connections in an electrically programmable memory circuit, a memory cell test device is proposed, this test consisting in reading the current traversing the read-accessed cells, the test device no longer using specific test connections between the cells and the corresponding input/output pins, but the operational connections of the read mode, between the read amplifiers and the input/output buffers, by short-circuiting the input and the output of the read amplifiers situated in a zone near the memory cells and of the input/output buffers situated in the peripheral zone, near the input/output pins. The means of short-circuiting the amplifiers and the buffers are situated in a zone near the memory cells and in the peripheral zone respectively.

公开(公告)号：EP3230984A1

公开(公告)日：2017-10-18

申请号：EP15868238.5

申请日：2015-11-06

Applicant: Intel Corporation

Inventor： ARSLAN, Umut ,  DRAY, Cyrille

IPC: G11C13/00

CPC classification number: G11C29/08 ,  G11C7/14 ,  G11C13/0033 ,  G11C13/0038 ,  G11C13/004 ,  G11C29/021 ,  G11C29/028 ,  G11C2029/5006

Abstract: Described is an apparatus comprising a leakage tracker to track leakage of a column of resistive memory cells; and a circuit for adjusting voltage on a SourceLine (SL) of the column of resistive memory cells. Described is also an apparatus comprising: a memory array having rows and columns of resistive memory cells; a leakage tracker to track leakage current of a column of resistive memory cells associated with the memory array; and a circuit, coupled to the leakage tracker, for adaptively boosting voltage on a SL of the column of resistive memory cells during read operation.

Abstract translation: 描述了一种包括泄漏跟踪器以跟踪一列电阻式存储器单元的泄漏的设备; 以及用于调整电阻式存储器单元的列的源线（SL）上的电压的电路。 还描述了一种装置，包括：具有电阻式存储器单元的行和列的存储器阵列; 泄漏跟踪器，用于跟踪与存储器阵列相关联的一列电阻式存储器单元的泄漏电流; 以及耦合到泄漏跟踪器的电路，用于在读操作期间自适应地升高电阻式存储单元列的SL上的电压。

公开(公告)号：EP1620859B1

公开(公告)日：2008-06-04

申请号：EP04751987.1

申请日：2004-05-12

Applicant: ECOLE POLYTECHNIQUE FEDERALE DE LAUSANNE (EPFL)

Inventor： PORTMANN, Lionel ,  KAYAL, Maher ,  PASTRE, Marc ,  BLAGOJEVIC, Marija ,  DECLERCQ, Michel

IPC: G11C7/14 ,  G11C11/4099 ,  G11C11/403 ,  G11C11/404 ,  G11C16/28

CPC classification number: G11C29/028 ,  G11C7/14 ,  G11C11/401 ,  G11C11/4099 ,  G11C16/28 ,  G11C29/02 ,  G11C29/12005 ,  G11C2029/5006 ,  G11C2211/4016

Abstract: There are many inventions described and illustrated herein. In a first aspect, the present invention is a technique and circuitry for reading data that is stored in memory cells. In one embodiment of this aspect, the present invention is a technique and circuitry for generating a reference current that is used, in conjunction with a sense amplifier, to read data that is stored in memory cells of a DRAM device. The technique and circuitry for generating a reference current may be implemented using an analog configuration, a digital configuration, and/or combinations of analog and digital configurations.

公开(公告)号：EP0836196B1

公开(公告)日：2006-05-24

申请号：EP97117402.4

申请日：1997-10-08

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： San, Kemal T. ,  Kaya, Cetin ,  Mehrad, Freidoon

IPC: G11C16/06 ,  G11C29/00

CPC classification number: G11C16/3409 ,  G06F2201/81 ,  G11C16/04 ,  G11C16/16 ,  G11C16/3404 ,  G11C16/3445 ,  G11C29/028 ,  G11C29/50 ,  G11C29/50004 ,  G11C2029/5006

Abstract: A system for testing and adjusting threshold voltages in flash EEPROMs is disclosed. The system includes a memory cell array (5) comprising a plurality of cell columns. Each cell column includes a plurality of memory cells (10). Each memory cell (10) has a control gate terminal (14), a drain terminal (12) and a source terminal 11. A control system comprising a wordline decoder (16), a column decoder (19) and a microprocessor (21) applies selected voltages to the respective terminals of the memory cells (10), and selects one of the plurality of cell columns for compaction verification. A detector (30) determines whether any one of the memory cells (10) of the selected cell column has a threshold voltage below a predetermined positive voltage, and supplies an output signal to the control system. The control system increases respective threshold voltages of the memory cells (10) of the selected cell column in response to the output signal of the detector (30).

公开(公告)号：EP1436815A1

公开(公告)日：2004-07-14

申请号：EP02759714.5

申请日：2002-09-17

Applicant: Kilopass Technologies, Inc.

Inventor： PENG, Jack Zezhong

IPC: G11C11/15

CPC classification number: H01L27/11206 ,  G11C11/5692 ,  G11C17/16 ,  G11C29/50 ,  G11C2029/5006 ,  H01L27/112 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor memory cell (300) having a data storage element (115) constructed around an ultra-thin dielectric (312) is used to store information by stressing the ultra-thin dielectric (312) into breakdown (soft or hard breakdown) to set the leakage current level of the memory cell (300). The memory cell (300) is read by sensing the current drawn by the cell (300). A suitable ultra-thin dielectric (312) is high quality gate oxide of about 50 Å thickness or less.

公开(公告)号：EP1361450A1

公开(公告)日：2003-11-12

申请号：EP02010478.2

申请日：2002-05-08

Applicant: Infineon Technologies AG

Inventor： Chee Hong, Liau, Eric

IPC: G01R31/30 ,  G11C29/00

CPC classification number: G11C29/56004 ,  G01R31/3004 ,  G11C29/50 ,  G11C29/56 ,  G11C2029/5006

Abstract: The present invention relates to a method for testing an electronic component (2), especially a memory chip, which is connected to a computer system (1). At first test patterns and AC-/DC-parameters are read into the computer system (1). Then the computer system (1) generates an input test pattern for the electronic component (2). After that, a simulation process is performed processing the input test pattern by the electronic component (2) and measuring the current flowing in the electronic component (2). Afterwards the input test pattern, the measured and the expected values of current are stored in the computer system (1). The generating of the input test pattern, the simulation process and the data storage are subsequently repeated for further AC- or DC-parameters, until all AC- or DC-parameters are processed. Finally, the stored data is analysed and a statement concerning the functionality of the tested electronic component (2) is made.

Abstract translation: 本发明涉及一种用于测试连接到计算机系统（1）的电子部件（2），特别是存储芯片的方法。 首先将测试模式和AC / DC参数读入计算机系统（1）。 然后，计算机系统（1）产生用于电子部件（2）的输入测试图案。 之后，通过电子部件（2）处理输入的测试图案并测量在电子部件（2）中流动的电流，进行模拟处理。 之后，输入测试模式，测量和预期的电流值存储在计算机系统（1）中。 随后重复生成输入测试模式，模拟过程和数据存储，以获得更多的AC或DC参数，直到处理所有AC或DC参数为止。 最后，对所存储的数据进行分析，并且对所测试的电子部件（2）的功能进行说明。

公开(公告)号：EP1333446A2

公开(公告)日：2003-08-06

申请号：EP03250538.0

申请日：2003-01-29

Applicant: STMicroelectronics, Inc.

Inventor： McClure, David C.

IPC: G11C29/00

CPC classification number: G11C29/50 ,  G11C11/22 ,  G11C2029/5006

Abstract: A test circuit and method are disclosed for testing memory cells of a ferroelectric memory device having an array of ferroelectric memory cells. The test circuitry is coupled to the bit lines, for selectively determining the voltage levels appearing on the bit lines based on a measured current level and providing externally to the ferroelectric memory device an electrical signal representative of the sensed voltage levels. In this way, ferroelectric memory cells exhibiting degraded performance may be identified.

Abstract translation: 公开了一种用于测试具有铁电存储器单元阵列的铁电存储器件的存储单元的测试电路和方法。 测试电路耦合到位线，用于基于测量的电流水平选择性地确定出现在位线上的电压电平，并且向铁电存储器件外部提供表示感测电压电平的电信号。 以这种方式，可以确定表现出降低性能的铁电存储单元。

公开(公告)号：EP0929895B1

公开(公告)日：2001-11-28

申请号：EP97910744.8

申请日：1997-09-29

Applicant: Advanced Micro Devices, Inc.

Inventor： HOLST, John, Christian ,  DRAPER, Donald, A.

IPC: G11C5/14

CPC classification number: G11C5/14 ,  G11C5/147 ,  G11C7/065 ,  G11C7/1006 ,  G11C7/12 ,  G11C7/22 ,  G11C8/08 ,  G11C8/14 ,  G11C11/401 ,  G11C11/4087 ,  G11C11/41 ,  G11C11/412 ,  G11C11/418 ,  G11C16/04 ,  G11C17/14 ,  G11C29/02 ,  G11C29/021 ,  G11C29/025 ,  G11C29/026 ,  G11C29/028 ,  G11C29/18 ,  G11C29/32 ,  G11C29/50 ,  G11C29/50004 ,  G11C29/50012 ,  G11C29/50016 ,  G11C2029/5004 ,  G11C2029/5006 ,  H03K3/356156 ,  H03K5/13 ,  H03K2005/00019 ,  H03K2005/00071 ,  H03L7/08 ,  H03L7/0995

Abstract: An active power supply filter effectively eliminates power supply noise using a resistive element and a capacitive element coupled at a node, and a switch with a control terminal controlled by the node. The active power supply filter is suitable for high frequency operation of a voltage-controlled oscillator (VCO) in a phase-locked loop (PLL) of a high-speed microprocessor. The active power supply filter removes VCO noise that would otherwise create jitter that reduces the effective clock cycle of the microprocessor. The active power supply filter is similarly useful in applications other than VCOs, PLLs, and microprocessors in which removal of substantial amounts of noise from the power supply is useful.