公开(公告)号：EP2540662B1

公开(公告)日：2018-08-08

申请号：EP12173032.9

申请日：2012-06-21

申请人： Samsung Electronics Co., Ltd.

发明人： Choi, Byoung-lyong ,  Lee, Eun-kyung ,  Whang, Dong-mok

IPC分类号： B82B1/00 ,  B82B3/00 ,  H01L29/10 ,  H01L29/775 ,  H01L29/16 ,  H01L29/06 ,  H01L29/66 ,  H01L21/02 ,  H01L29/78 ,  H01L29/786

CPC分类号： H01L29/1606 ,  B82Y10/00 ,  B82Y30/00 ,  B82Y40/00 ,  H01L21/02164 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02491 ,  H01L21/02527 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/02645 ,  H01L29/0673 ,  H01L29/66045 ,  H01L29/66439 ,  H01L29/66742 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78684 ,  H01L29/78696

摘要： A graphene structure and a method of manufacturing the graphene structure, and a graphene device and a method of manufacturing the graphene device. The graphene structure includes a substrate; a growth layer disposed on the substrate and having exposed side surfaces; and a graphene layer disposed on the side surfaces of the growth layer. A growth layer 120 and a protective layer 130 are sequentially formed on a substrate 110. The growth layer 120 is a layer from which a graphene layer 140 grows, and may be formed of for example, metal or germanium (Ge). The growth layer 120 may have a thickness of, for example, about several nanometers. As will be described later, the thickness of the growth layer 120 determines a width W of the graphene layer 140. Then, the protective layer 130 is formed on an upper surface of the growth layer 120. A groove 150 is formed in the protective layer 130 and the growth layer 120. The groove 150 is formed in a predetermined shape by sequentially etching the protective layer 130 and the growth layer 120. The groove 150 exposes side surfaces of the protective layer 130 and the growth layer 120 and an upper surface of the substrate 110. The groove 150 may be formed by etching the protective layer 130 and the growth layer 120 by using an etching mask until the upper surface of the substrate 110 is exposed. FIG. 3A is a perspective view showing that the graphene layer 140 is grown from the side surfaces of the growth layer 120.

公开(公告)号：EP3339244A1

公开(公告)日：2018-06-27

申请号：EP16205939.8

申请日：2016-12-21

申请人： IMEC vzw

发明人： HORIGUCHI, Naoto ,  HIKAVYY, Andriy ,  DEMUYNCK, Steven

IPC分类号： B82Y10/00 ,  H01L29/40 ,  H01L29/417 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L29/06 ,  H01L29/41 ,  H01L29/04

CPC分类号： H01L21/823871 ,  B82Y10/00 ,  H01L21/02603 ,  H01L21/30604 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/045 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/401 ,  H01L29/413 ,  H01L29/417 ,  H01L29/41791 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/78618 ,  H01L29/78696 ,  H01L2029/7858

摘要： A method for making a contact (900) to a source or drain region of a nanowire- or fin-FET semiconductor device, comprising:
a. providing the semiconductor device having at least one fin-shaped source or drain region, the source or drain region having an exposed area,
b. partially etching the source or drain region such that the exposed area is increased, by creating a groove in the top-surface (810; Fig. 8a), the side-surface (820; Fig. 2b) or completely dividing the fin-shaped source or drain region into a stack of nanowires (830; Fig. 2c), and
c. providing a contact (900) covering at least the etched part (810; 820; 830) of the source or drain region; wherein the contact (900) contacts the source or drain region on at least 3 sides of the source or drain region.

公开(公告)号：EP3198650A4

公开(公告)日：2018-05-16

申请号：EP14902459

申请日：2014-09-26

申请人： INTEL CORP

发明人： RIOS RAFAEL ,  KUHN KELIN J ,  KIM SEIYON ,  WEBER JUSTIN R

IPC分类号： H01L29/78 ,  H01L21/335 ,  H01L29/12 ,  H01L29/16 ,  H01L29/66 ,  H01L29/775 ,  H01L49/00

CPC分类号： H01L29/66439 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/122 ,  H01L29/16 ,  H01L29/20 ,  H01L29/24 ,  H01L29/42356 ,  H01L29/42364 ,  H01L29/4238 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/66742 ,  H01L29/66969 ,  H01L29/775 ,  H01L29/778 ,  H01L29/78636 ,  H01L29/78681 ,  H01L29/78684 ,  H01L29/78696 ,  H01L49/00

摘要： Embodiments of the invention include metal oxide metal field effect transistors (MOMFETs) and methods of making such devices. In embodiments, the MOMFET device includes a source and a drain with a channel disposed between the source and the drain. According to an embodiment, the channel has at least one confined dimension that produces a quantum confinement effect in the channel. In an embodiment, the MOMFET device also includes a gate electrode that is separated from the channel by a gate dielectric. According to embodiments, the band-gap energy of the channel may be modulated by changing the size of the channel, the material used for the channel, and/or the surface termination applied to the channel. Embodiments also include forming an type device and a P-type device by controlling the work-function of the source and drain relative to the conduction band and valance band energies of the channel.

公开(公告)号：EP3301073A1

公开(公告)日：2018-04-04

申请号：EP17192411.1

申请日：2017-09-21

申请人： Semiconductor Manufacturing International Corporation (Beijing) ,  Semiconductor Manufacturing International Corporation (Shanghai)

发明人： ZHOU, Ming

IPC分类号： B82Y10/00 ,  B82Y40/00 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/06

CPC分类号： H01L29/0673 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/02164 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/3247 ,  H01L21/67069 ,  H01L29/0847 ,  H01L29/401 ,  H01L29/42376 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785 ,  H01L29/786

摘要： A method for manufacturing a semiconductor device includes providing a semiconductor substrate (201), performing an etch process on the semiconductor substrate to form a fin (2011) and a trench on opposite sides of the fin, forming an etch guide layer (204), preferably made of silicon oxide, filling the trench, performing an etch process on the etch guide layer to expose a first portion of the fin (20111), and selectively etching the exposed first portion of the fin to remove a portion of the exposed portion of the fin adjacent to an upper first surface of the etch guide layer to form a first nanowire (211). The method further includes repeating the etch process and the selectively etching process to sequentially form second and third nanowires (212, 213), and forming a gate structure (220) surrounding the nanowire. The first, second, and third nanowires are formed in the direction perpendicular to the semiconductor substrate.

摘要翻译： 一种用于制造半导体器件的方法包括：提供半导体衬底（201），在半导体衬底上执行蚀刻工艺以在鳍的相对侧上形成鳍（2011）和沟槽，形成蚀刻引导层（204） 优选地由氧化硅制成，填充沟槽，在蚀刻引导层上执行蚀刻工艺以暴露鳍状物（20111）的第一部分，并且选择性地蚀刻鳍状物的暴露的第一部分以去除暴露的部分的 所述鳍状物邻近所述蚀刻引导层的上部第一表面以形成第一纳米线（211）。 该方法进一步包括重复蚀刻工艺和选择性蚀刻工艺以顺序地形成第二和第三纳米线（212,213），并且形成围绕纳米线的栅极结构（220）。 第一，第二和第三纳米线沿垂直于半导体衬底的方向形成。

公开(公告)号：EP3262682A1

公开(公告)日：2018-01-03

申请号：EP16703005.5

申请日：2016-01-11

申请人： Qualcomm Incorporated

发明人： MACHKAOUTSAN, Valdimir ,  BADAROGLU, Mustafa ,  XU, Jeffrey Junhao ,  SONG, Stanley Seungchul ,  YEAP, Choh Fei

IPC分类号： H01L27/088 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/775 ,  B82Y10/00

CPC分类号： H01L21/823828 ,  B82Y10/00 ,  H01L21/321 ,  H01L21/32133 ,  H01L21/823437 ,  H01L21/82345 ,  H01L21/823481 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823878 ,  H01L27/0883 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/0642 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66803 ,  H01L29/775 ,  H01L29/785

摘要： An integrated circuit (IC) device may include a first active transistor of a first-type in a first-type region. The first active transistor may have a first-type work function material and a low channel dopant concentration in an active portion of the first active transistor. The IC device may also include a first isolation transistor of the first-type in the first-type region. The second active transistor may have a second-type work function material and the low channel dopant concentration in an active portion of the first isolation transistor. The first isolation transistor may be arranged adjacent to the first active transistor.

公开(公告)号：EP3050076A4

公开(公告)日：2017-10-18

申请号：EP13894081

申请日：2013-09-27

申请人： INTEL CORP

发明人： HAFEZ WALID ,  LEE CHEN-GUAN ,  JAN CHIA-HONG

IPC分类号： H01C7/06 ,  H01C17/232 ,  H01L27/06 ,  H01L29/66 ,  H01L29/775 ,  H01L49/02

CPC分类号： H01L27/0629 ,  H01C7/06 ,  H01C17/232 ,  H01L28/20 ,  H01L28/24 ,  H01L29/66439 ,  H01L29/66469 ,  H01L29/775

摘要： Methods of forming resistor structures with tunable temperature coefficient of resistance are described. Those methods and structures may include forming an opening in a resistor material adjacent source/drain openings on a device substrate, forming a dielectric material between the resistor material and the source/drain openings, and modifying the resistor material, wherein a temperature coefficient resistance (TCR) of the resistor material is tuned by the modification. The modifications include adjusting a length of the resistor, forming a compound resistor structure, and forming a replacement resistor.

公开(公告)号：EP2250124B1

公开(公告)日：2017-03-29

申请号：EP08872245.9

申请日：2008-12-09

申请人： Qucor Pty Ltd

发明人： SIMMONS, Michelle, Yvonne ,  FUHRER, Andreas ,  FUECHSLE, Martin ,  WEBER, Bent ,  REUSCH, Thilo, Curd, Gerhard ,  POK, Wilson ,  RUESS, Frank

IPC分类号： B82B3/00 ,  H01L21/28 ,  B82B1/00 ,  H01L21/31

CPC分类号： H01L23/544 ,  B82B3/0019 ,  B82Y10/00 ,  H01L29/66439 ,  H01L2924/0002 ,  H01L2924/00

公开(公告)号：EP3069377A1

公开(公告)日：2016-09-21

申请号：EP14862401.8

申请日：2014-11-13

申请人： Michigan Technological University

发明人： DAUNAIS, Thomas ,  BERGSTROM, Paul L.

IPC分类号： H01L21/00

CPC分类号： G01N33/54386 ,  B82Y10/00 ,  B82Y40/00 ,  G01N27/127 ,  G01N27/4146 ,  G01N33/552 ,  G01N33/56916 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02236 ,  H01L21/02255 ,  H01L21/02266 ,  H01L21/0273 ,  H01L21/30604 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/311 ,  H01L29/0673 ,  H01L29/16 ,  H01L29/66439 ,  H01L29/775

摘要： A method for fabricating silicon nanowires. The method includes the steps of: depositing a silicon nitride layer on a silicon on insulator (SOI) starting wafer; patterning the silicon nitride to define at least one silicon microbar; etching the SOI starting wafer to expose the at least one silicon microbar, wherein the at least one microbar is surrounded by a raised perimeter; growing a silicon oxide layer on the raised perimeter of the at least one microbar; and etching a portion of the at least one silicon microbar to produce at least one silicon nanowire adjacent the silicon oxide layer.

公开(公告)号：EP3050076A1

公开(公告)日：2016-08-03

申请号：EP13894081.2

申请日：2013-09-27

申请人： Intel Corporation

发明人： HAFEZ, Walid ,  LEE, Chen-Guan ,  JAN, Chia-Hong

IPC分类号： H01L21/027 ,  H01L21/265 ,  H01L21/336

CPC分类号： H01L27/0629 ,  H01C7/06 ,  H01C17/232 ,  H01L28/20 ,  H01L28/24 ,  H01L29/66439 ,  H01L29/66469 ,  H01L29/775

摘要： Methods of forming resistor structures with tunable temperature coefficient of resistance are described. Those methods and structures may include forming an opening in a resistor material adjacent source/drain openings on a device substrate, forming a dielectric material between the resistor material and the source/drain openings, and modifying the resistor material, wherein a temperature coefficient resistance (TCR) of the resistor material is tuned by the modification. The modifications include adjusting a length of the resistor, forming a compound resistor structure, and forming a replacement resistor.

摘要翻译： 形成具有电阻的可调温度系数电阻器结构的方法进行了描述。 （这些方法和结构可包括在一个电阻器材料上的器件衬底相邻的源极/漏极开口开口形成，形成电阻材料和所述源极/漏极开口之间的介电材料，以及修改所述电阻材料，worin温度系数电阻 电阻器材料的TCR）是由改性调谐。 所述修饰包括调节电阻器的长度，从而形成一个复合电阻器的结构，并且形成电阻器替代。

公开(公告)号：EP2513972B1

公开(公告)日：2016-05-04

申请号：EP10838069.2

申请日：2010-11-03

申请人： Intel Corporation

发明人： SHAH, Uday ,  CHU-KUNG, Benjamin ,  JIN, Been-Yih ,  PILLARISETTY, Ravi ,  RADOSAVLJEVIC, Marko ,  RACHMADY, Willy

IPC分类号： H01L29/775 ,  H01L29/06 ,  H01L29/16 ,  H01L29/78 ,  H01L21/02 ,  H01L21/20 ,  H01L21/336 ,  H01L29/66 ,  B82Y10/00 ,  B82Y40/00

CPC分类号： H01L29/0665 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/02236 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/76224 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78 ,  H01L29/78696 ,  H01L2221/1094