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    SHALLOW TRENCH ISOLATING STRUCTURE HAVING AN AIR GAP, A CMOS IMAGE SENSOR EMPLOYING THE SAME, AND A PRODUCTION METHOD THEREFOR
    33.
    发明公开
    SHALLOW TRENCH ISOLATING STRUCTURE HAVING AN AIR GAP, A CMOS IMAGE SENSOR EMPLOYING THE SAME, AND A PRODUCTION METHOD THEREFOR 审中-公开
    FLACHE GRABENISOIERUNGSSTRUKTUR MIT LUFTSPALT，CMOS-BILDSENSOR DAMIT UND HERSTELLUNGSVERFAHRENDAFÜR

    公开(公告)号：EP2323161A2

    公开(公告)日：2011-05-18

    申请号：EP09810200.7

    申请日：2009-08-27

    申请人： Crosstek Capital, LLC

    发明人： SUNG, Nag Kyun

    IPC分类号： H01L21/76

    CPC分类号： H01L21/764 ,  H01L21/76224 ,  H01L21/823481 ,  H01L27/1463 ,  H01L27/14643 ,  H01L27/14689

    摘要： Disclosed is a shallow trench isolation structure having an air gap for suppressing the dark currents and cross-talk which occur in CMOS image sensors. The shallow trench isolation structure suppresses photons injected from neighboring pixels and dark current, so that high-quality images are obtained. Since impurities are removed from a p type ion implantation region for a photodiode when an inner wall oxide layer is etched to form the air gap, the p type ion implantation region has a uniform doping profile, thereby suppressing the diffusion of electrons towards the surface and achieving an image having a high quality.

    摘要翻译： 公开了一种浅沟槽隔离结构，其具有用于抑制CMOS图像传感器中发生的暗电流和串扰的气隙。 浅沟槽隔离结构抑制从相邻像素注入的光子和暗电流，从而获得高质量的图像。 由于当蚀刻内壁氧化物层以形成气隙时，从用于光电二极管的ap型离子注入区域去除杂质，所以p型离子注入区域具有均匀的掺杂分布，从而抑制电子向表面的扩散，并实现 具有高质量的图像。

    Integrated device with both SOI insulation and junction insulation and manufacturing method
    34.
    发明公开
    Integrated device with both SOI insulation and junction insulation and manufacturing method 审中-公开

    公开(公告)号：EP2264753A3

    公开(公告)日：2011-04-20

    申请号：EP10183038.8

    申请日：2006-06-27

    申请人： STMicroelectronics S.r.l.

    发明人： Montanini, Pietro ,  Ammendola, Giuseppe ,  Depetro, Riccardo ,  Mottura, Marta

    IPC分类号： H01L21/76 ,  H01L21/84 ,  H01L27/12 ,  H01L21/762

    CPC分类号： H01L21/84 ,  H01L21/26586 ,  H01L21/3226 ,  H01L21/76264 ,  H01L27/1207

    摘要： A method is proposed for manufacturing an integrated electronic device (500). The method includes the steps of providing an SOI substrate (505) including a semiconductor substrate (510), an insulating layer (515) on the semiconductor substrate, and a semiconductor starting layer (512) on the insulating layer, the substrate and the starting layer being of a first type of conductivity, performing an epitaxial growing process, the epitaxial growing process being applied to the starting layer to obtain a thicker semiconductor active layer (542) of the first type of conductivity embedding the starting layer on the insulating layer, forming at least one insulating trench (558) extending from an exposed surface of the active layer to the insulating layer, the at least one insulating trench partitioning the active layer into insulated regions (560) and at least one further insulated region (561), and integrating components (580) of the device in the insulated regions, the components being insulated from the substrate by the insulating layer; in the solution according to an embodiment of the invention, the method further includes, before the step of performing an epitaxial growing process, forming at least one contact trench (520) extending from an exposed surface of the starting layer to the substrate in correspondence to each further insulated region, each contact trench clearing a corresponding portion (530b,530s) of the starting layer, of the insulating layer and of the substrate, implanting dopants of a second type of conductivity different from the first type into at least part of the cleared portions, wherein the epitaxial growing is further applied to the cleared portions thereby at least partially filling each contact trench with semiconductor material, the dopants diffusing during the epitaxial growing to form an insulating region (545) of the second type of conductivity enclosing the at least one contact trench of each further insulated region, and integrating further components (580) of the device in each further insulated region, the further components being insulated from the substrate by a junction formed by the corresponding insulating region with the active layer and/or the substrate when reverse-biased.

    SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME
    40.
    发明公开
    SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME 审中-公开
    HALBLEITERBAUELEMENT UND HERSTELLUNGSVERFAHRENDAFÜR

    公开(公告)号：EP1756949A4

    公开(公告)日：2009-07-08

    申请号：EP05732887

    申请日：2005-04-06

    申请人： FREESCALE SEMICONDUCTOR INC

    发明人： ZHU RONGHUA ,  BOSE AMITAVA ,  KHEMKA VISHNU K ,  PARTHASARATHY VIJAY

    IPC分类号： H03K17/60 ,  G06F13/00 ,  H01L21/20 ,  H01L21/76 ,  H01L23/62 ,  H01L27/02 ,  H01L29/739 ,  H01L29/861

    CPC分类号： H01L29/7391 ,  H01L29/861

    摘要： In one embodiment, semiconductor device 10 comprises a diode which uses isolation regions (34, 16, and 13) and a plurality of dopant concentrations (30, 20, 24, and 26) which may be used to limit the parasitic current that is injected into the semiconductor substrate (12). Various biases on the isolation regions (34, 16, and 13) may be used to affect the behavior of semiconductor device (10). In addition, a conductive layer (28) may be formed overlying the junction between anode (42) and cathode (40). This conductive layer (28) may decrease the electric field in selected regions in order to increase the maximum voltage that may be applied to cathode (40).

    摘要翻译： 在一个实施例中，半导体器件10包括二极管，其使用可用于限制注入的寄生电流的隔离区（34,16和13）和多个掺杂剂浓度（30,20,24和26） 进入半导体衬底（12）。 可以使用隔离区（34,16和13）上的各种偏压来影响半导体器件（10）的行为。 另外，导电层（28）可以形成为覆盖阳极（42）和阴极（40）之间的结。 该导电层（28）可以减小选定区域中的电场，以便增加可以施加到阴极（40）的最大电压。