公开(公告)号：EP2728976A1

公开(公告)日：2014-05-07

申请号：EP13190224.9

申请日：2013-10-25

申请人： STMicroelectronics S.r.l. ,  Freescale Semiconductor, Inc.

发明人： Rotigni, Mario ,  Moseley, Richard ,  Bhatt, Piyush ,  Edgington, Gregory C.

IPC分类号： H05K1/02

CPC分类号： H05K1/0231 ,  H05K1/0262 ,  H05K1/0298 ,  H05K2201/09309 ,  H05K2201/09327 ,  H05K2201/09336 ,  H05K2201/09345

摘要： It is described a printed circuit board (50). The board comprises a first outer layer (23), a second outer layer (20) and an integrated circuit (2) mounted on the second outer layer. The integrated circuit has a single exposed pad (1) electrically connected to a ground reference, it has a first supply pin (5) electrically connected to a first power supply (VCC1) and it has a second supply pin (105) electrically connected to a second power supply, wherein the first power supply is configured to generate a first supply current with frequency components higher than the frequency components of a second supply current generated by the second power supply. The board further comprises a first decoupling capacitor (3) mounted on the second outer layer in the proximity of the first supply pin (5), the first decoupling capacitor having a first terminal (8) electrically connected with the first supply pin (5) and having a second terminal (9), it comprises an inner layer (21) interposed between the first outer layer (23) and the second outer layer (20), the inner layer comprising a metal layer (4) electrically connected to said ground reference, it comprises a first Via (7-1) configured to electrically connect the exposed pad (1) with the metal layer (4) of the inner layer, it comprises a second Via (6) configured to electrically connect the second terminal (9) of the first decoupling capacitor with the metal layer (4) of the inner layer and it comprises a second decoupling capacitor (173) having a first pin (278) electrically connected to the second power supply and having a second pin (279) electrically connected to said ground reference.

摘要翻译： 描述了印刷电路板（50）。 板包括安装在第二外层上的第一外层（23），第二外层（20）和集成电路（2）。 集成电路具有电连接到接地基准的单个裸露焊盘（1），其具有电连接到第一电源（VCC1）的第一电源引脚（5），并且其具有电连接到 第二电源，其中所述第一电源被配置为产生具有高于由所述第二电源产生的第二电源电流的频率分量的频率分量的第一电源电流。 该板还包括安装在第二外层附近的第一电源引脚（5）的第一去耦电容器（3），第一去耦电容器具有与第一电源引脚（5）电连接的第一端子（8） 并且具有第二端子（9），其包括介于所述第一外层（23）和所述第二外层（20）之间的内层（21），所述内层包括电连接到所述地面的金属层（4） 参考，它包括被配置为将暴露的焊盘（1）与内层的金属层（4）电连接的第一通孔（7-1），其包括构造成电连接第二端子的第二通孔（6） 第一去耦电容器与内层的金属层（4）的第二去耦电容器（173），并且其包括第二去耦电容器（173），其具有电连接到第二电源并具有第二引脚（279）的第一引脚（278） 电连接到所述接地基准。

公开(公告)号：EP2728582A1

公开(公告)日：2014-05-07

申请号：EP13188548.5

申请日：2013-10-14

申请人： Freescale Semiconductor, Inc.

发明人： MULLER, Gilles J. ,  SYZDEK, Ronald J.

IPC分类号： G11C16/04 ,  G11C16/08 ,  G11C16/26

CPC分类号： G11C8/08 ,  G11C16/0425 ,  G11C16/0433 ,  G11C16/08 ,  G11C16/26 ,  G11C16/30

摘要： A memory (101) having an array (103) of multi-gate memory cells and a word line driver circuit (115) coupled to a sector of memory cells of the array. In at least one mode of operation, the word line driver circuit is controllable to place an associated control gate word line coupled to the control gate word line driver and coupled to the sector in a floating state during a read operation where the sector is a non selected sector.

摘要翻译： 具有多栅极存储单元的阵列（103）的存储器（101）和耦合到阵列的存储器单元的扇区的字线驱动电路（115）。 在至少一种操作模式中，字线驱动器电路是可控制的，以将耦合到控制栅极字线驱动器的相关联的控制栅极字线在读取操作期间以浮动状态耦合到扇区，其中扇区是非 选定部门。

公开(公告)号：EP2722882A2

公开(公告)日：2014-04-23

申请号：EP13183320.4

申请日：2013-09-06

申请人： Freescale Semiconductor, Inc.

发明人： Viswanathan, Lakshminarayan ,  Jones, Jeffrey ,  Marshall, Scott D.

IPC分类号： H01L23/66

CPC分类号： H01L23/66 ,  H01L23/047 ,  H01L23/49589 ,  H01L24/48 ,  H01L24/49 ,  H01L2223/6611 ,  H01L2223/6655 ,  H01L2223/6672 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/49052 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/30111 ,  H01L2924/00 ,  H01L2224/45099

摘要： Embodiments of semiconductor devices (100, 300, 600, 700, 800, 900, 1100) (e.g., RF devices) include a substrate (306, 606, 706, 806, 906, 1106), an isolation structure (308, 608, 708, 808, 908, 1108), an active device (120, 320, 620, 720, 820, 920, 1120), a lead (104, 304, 604, 704, 804, 904, 1104), and a circuit (149, 150, 349, 350, 649, 650, 749, 750, 849, 850, 949, 950). The isolation structure is coupled to the substrate, and includes an opening. An active device area is defined by a portion of the substrate surface that is exposed through the opening. The active device is coupled to the substrate surface within the active device area. The circuit is electrically coupled between the active device and the lead. The circuit includes one or more elements (136, 138, 144, 146, 338, 344, 638, 644, 738, 744, 838, 844, 846, 936, 938, 944, 946, 1136, 1146) positioned outside the active device area (e.g., physically coupled to the isolation structure and/or under the lead). The elements positioned outside the active device area may include elements of an envelope termination circuit (149, 349, 649, 749, 849, 949) and/or an impedance matching circuit (150, 350, 650, 750, 850, 950). Embodiments also include method (1202, 1204, 1206, 1208, 1210) of manufacturing such semiconductor devices.

摘要翻译： 半导体装置的实施例（100，300，600，700，800，900，1100）（例如，RF）装置包括一个基片（306，606，706，806，906，1106），在隔离结构（308，608， （708，808，908，1108）有源器件（120，320，620，720，820，920，1120），铅（104，304，604，704，804，904，1104），和一个电路上 149，150，349，350，649，650，749，750，849，850，949，950）。 隔离结构耦合到所述基底，并且包括开口。 的有源器件区域由基材表面的一部分所限定并通过开口露出。 有源器件在有源器件区域内耦合到所述衬底的表面。 该电路电耦合在有源器件和引线之间。 该电路包括以外的活性定位一个或多个元素（136，138，144，146，338，344，638，644，738，744，838，844，846，936，938，944，946，1136，1146） 设备区域（例如，物理耦合到所述隔离结构和/或下的铅）。 有源器件区域的外部定位在所述元件可以包括一个包络终端电路（149，349，649，749，849，949）和/或阻抗匹配电路（150，350，650，750，850，950）的元件。 因此，实施例包括检查半导体器件的制造方法（1202，1204，1206，1208，1210）。

公开(公告)号：EP2294580B1

公开(公告)日：2014-04-02

申请号：EP08776432.0

申请日：2008-06-20

申请人： Freescale Semiconductor, Inc.

发明人： ROHLEDER, Michael ,  HAY, Gary ,  MUELLER, Stephan ,  THANNER, Manfred

IPC分类号： G11C29/00 ,  G06F11/16

CPC分类号： G06F11/167 ,  G11C29/74 ,  G11C2029/0411

公开(公告)号：EP2709144A2

公开(公告)日：2014-03-19

申请号：EP13183374.1

申请日：2013-09-06

申请人： Freescale Semiconductor, Inc.

发明人： Leal, George R ,  Pham, Tim V

IPC分类号： H01L21/56 ,  H01L23/433 ,  H01L23/00

CPC分类号： H01L23/49568 ,  H01L21/561 ,  H01L21/565 ,  H01L21/566 ,  H01L23/3107 ,  H01L23/3675 ,  H01L23/3736 ,  H01L23/4334 ,  H01L23/49541 ,  H01L23/49838 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L24/97 ,  H01L25/0655 ,  H01L2224/16225 ,  H01L2224/29191 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/92225 ,  H01L2224/97 ,  H01L2924/12042 ,  H01L2924/141 ,  H01L2924/14335 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/17738 ,  H01L2924/17747 ,  H01L2924/181 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2924/00

摘要： A method and apparatus are provided for manufacturing a lead frame based thermally enhanced flip chip package with an exposed heat spreader lid array (310) designed for direct attachment to an array of integrated circuit die (306) by including a thermal interface adhesion layer (308) to each die (306) and encapsulating the attached heat spreader lid array (310) and array of integrated circuit die (306) with mold compound (321) except for planar upper lid surfaces of the heat spreader lids (312).

摘要翻译： 提供了一种用于制造具有暴露的散热器盖阵列（310）的基于引线框架的热增强倒装芯片封装的方法和设备，所述裸露散热器盖阵列（310）通过包括热界面粘附层（308）而被设计用于直接附接到集成电路裸片（306） ）到除了散热器盖（312）的平坦上盖表面之外的每个管芯（306）并且用附接模制化合物（321）封装附接的散热器盖阵列（310）和集成电路管芯阵列（306）。

公开(公告)号：EP2620945A3

公开(公告)日：2014-03-19

申请号：EP13151698.1

申请日：2013-01-17

申请人： Freescale Semiconductor, Inc.

发明人： Mu, Fuchen ,  Wang, Yanzhuo

IPC分类号： G11C16/34 ,  G11C16/04 ,  H01L29/792 ,  H01L21/28 ,  H01L21/3105

CPC分类号： G11C16/0416 ,  G11C16/0483 ,  G11C16/349 ,  H01L21/28273

摘要： A semiconductor device comprises an array (12) of memory cells (18). Each of the memory cells includes a tunnel dielectric (26), a well region including a first current electrode (28) and a second current electrode (30), and a control gate (20). The first and second current electrodes are adjacent one side of the tunnel dielectric (26) and the control gate is adjacent another side of the tunnel dielectric. A controller (16) is coupled to the memory cells (18). The controller (16) includes logic to determine when to perform a healing process in the tunnel dielectric (26) of the memory cells (18), and to apply a first voltage to the first current electrode (28) of the memory cells (18) during the healing process to remove trapped electrons and holes from the tunnel dielectric (26).

公开(公告)号：EP2704150A2

公开(公告)日：2014-03-05

申请号：EP13179567.6

申请日：2013-08-07

申请人： Freescale Semiconductor, Inc.

发明人： Mu, Fuchen ,  Wang, Yanzhuo

IPC分类号： G11C16/34

CPC分类号： G11C16/3468

摘要： A semiconductor memory device (10) comprises a memory controller (12), and an array of memory cells (20) coupled to communicate with the memory controller. The memory controller is configured to perform a first soft program operation (56) using first soft program voltages and a first soft program verify level, and determine whether a first charge trapping threshold has been reached (54). When the first charge trapping threshold has been reached, a second soft program operation (56) is performed using second soft program voltages and a second soft program verify level.

摘要翻译： 半导体存储器件（10）包括存储器控制器（12）和耦合以与存储器控制器通信的存储器单元阵列（20）。 存储器控制器被配置为使用第一软编程电压和第一软程序验证电平来执行第一软编程操作（56），并且确定是否已经达到第一电荷捕获阈值（54）。 当达到第一电荷捕获阈值时，使用第二软编程电压和第二软程序验证电平来执行第二软编程操作（56）。

公开(公告)号：EP2700202A1

公开(公告)日：2014-02-26

申请号：EP11863817.0

申请日：2011-04-20

申请人： Freescale Semiconductor, Inc.

发明人： EDMISTON, Graham

IPC分类号： H04L12/56

CPC分类号： H04L47/623 ,  H04L45/40 ,  H04L49/1546 ,  H04L49/251 ,  H04L49/257

摘要： An integrated circuit device (205) comprising at least one cut-through forwarding module (200). The cut-through forwarding module (200) comprises at least one receiver component (210) arranged to receive data to be forwarded, and to generate a request (212) for transmission of a block of data upon receipt thereof, and at least one controller unit (220) arranged to execute at least one thread (225, 310, 320, 330, 340, 350) for processing requests generated by the at least one receiver component (210). The at least one controller unit (220) is arranged to set a priority context for the at least one thread (225, 310, 320, 330, 340, 350), and to schedule an execution of the at least one thread based at least partly on the priority context therefor.

公开(公告)号：EP2700158A1

公开(公告)日：2014-02-26

申请号：EP11729462.9

申请日：2011-04-20

申请人： Freescale Semiconductor, Inc.

发明人： NOORI, Basim ,  BOUISSE, Gerard ,  JONES, Jeffrey ,  NANAN, Jean-Christophe ,  PLA, Jaime

IPC分类号： H03F1/02

CPC分类号： H03F1/565 ,  H01L2224/49175 ,  H03F1/0288 ,  H03F3/195 ,  H03F3/21 ,  H03F3/68 ,  H03F2200/222 ,  H03F2200/387 ,  H03F2200/423 ,  H03F2200/451

摘要： Apparatus are provided for amplifier systems and related circuits are provided. An exemplary circuit includes a main amplifier arrangement, first impedance matching circuitry coupled between the output of the main amplifier arrangement and a first circuit output, a peaking amplifier arrangement, and second impedance matching circuitry coupled between the output of the peaking amplifier arrangement and a second output of the circuit. In one exemplary embodiment, the first impedance matching circuitry and the second impedance matching circuitry have different circuit topologies and different physical topologies.

摘要翻译： 提供放大器系统的装置，并提供相关的集成电路。 示例性集成电路包括主放大器装置，耦合在主放大器装置的输出端和集成电路的第一输出端之间的第一阻抗匹配电路，峰值放大器装置和耦合在峰化放大器的输出端之间的第二阻抗匹配电路 布置和集成电路的第二输出。 在一个示例性实施例中，第一阻抗匹配电路和第二阻抗匹配电路具有不同的电路拓扑和不同的物理拓扑。

公开(公告)号：EP2699453A1

公开(公告)日：2014-02-26

申请号：EP11729469.4

申请日：2011-04-22

申请人： Freescale Semiconductor, Inc.

发明人： HEMON, Erwan ,  AHMED, Hamada ,  TURPIN, Pierre

IPC分类号： B60R21/017 ,  G01R27/26

CPC分类号： G01R31/028 ,  B60R21/0173 ,  G01R31/006 ,  G01R31/016

摘要： A method of measuring a capacitor value comprises the steps of loading (61) the capacitor (125) up to a given voltage value (Vboost); obtaining (62) a first measure (T1) of a time for discharging the capacitor by a fixed voltage drop (dV), the discharge of the capacitor being caused by a first current; reloading (63) the capacitor up to the given voltage value; obtaining (64) a second measure (t2) of a time for discharging the capacitor by the fixed voltage drop, the discharge of the capacitor being caused by the first current and by a second current of known value (I_pd) added to said first current; and determining (65) the capacitor value from the difference between the first measure and the second measure, based on the given voltage drop or the given time, respectively, and based further on the known value of the given second current. Application to the diagnosis of the reservoir capacitor of vehicle safety systems.