公开(公告)号：EP1455557B1

公开(公告)日：2013-02-27

申请号：EP03023937.0

申请日：2003-10-22

Applicant: ROBERT BOSCH GMBH

Inventor： Roozenbeck, Herman ,  Bayer, Uwe

IPC: H05K1/02 ,  H05K1/11

CPC classification number: H05K1/0216 ,  H05K1/0231 ,  H05K1/115 ,  H05K1/117 ,  H05K1/18 ,  H05K2201/0715 ,  H05K2201/09254 ,  H05K2201/09318 ,  H05K2201/09345 ,  H05K2201/09627 ,  H05K2201/10689

公开(公告)号：EP1455557A2

公开(公告)日：2004-09-08

申请号：EP03023937.0

申请日：2003-10-22

Applicant: ROBERT BOSCH GMBH

Inventor： Roozenbeck, Herman ,  Bayer, Uwe

IPC: H05K1/02

CPC classification number: H05K1/0216 ,  H05K1/0231 ,  H05K1/115 ,  H05K1/117 ,  H05K1/18 ,  H05K2201/0715 ,  H05K2201/09254 ,  H05K2201/09318 ,  H05K2201/09345 ,  H05K2201/09627 ,  H05K2201/10689

Abstract: Die vorliegende Erfindung stellt eine Trägervorrichtung (10) für elektrische Bauelemente bereit mit: einer ersten leitfähigen Ebene (23') zum Bereitstellen eines Bezugspotentials (23); und mindestens einer elektrisch von der ersten Ebene (23') isolierten zweiten Ebene (11') mit strukturierten Leitungen (11) zum Anbinden elektrischer Anschlusseinrichtungen (12) externer Bauelemente und zum Anbinden interner Bauelemente auf der Trägervorrichtung (10), wobei die Leitungen (11) zum Anbinden elektrischer Anschlusseinrichtungen (12) externer analoger Bauelemente und/oder Sensoren Bezugspotentialleitungen (16, 17) aufweisen, welche sich an einem ersten Stempunkt (18) sammeln, und die Leitungen (11) zum Anbinden interner Bauelemente Bezugspotentialleitungen (19, 20, 21) aufweisen, welche sich an einem zweiten Sternpunkt (22) sammeln und über mindestens eine Durchkontaktierungseinrichtung (23") mit der ersten Ebene (23') galvanisch gekoppelt sind und/oder die Durchkontaktierungseinrichtung (23") den ersten und/oder zweiten Stempunkt (18, 22) bildet.

Abstract translation: 矩形电路板（10）在形成在表面（11'）上的多个导体（11）的点（18,22）处具有在平坦顶部和底部表面之间的连接（23）。 电子电路的构造块包括电容器（26）和功能计算器（13）。 板上的端子（12）接收外部模拟信号n（14）和n + 1（15）和参考电位n（16）和n + 1（17）。

公开(公告)号：EP2728976A1

公开(公告)日：2014-05-07

申请号：EP13190224.9

申请日：2013-10-25

Applicant: STMicroelectronics S.r.l. ,  Freescale Semiconductor, Inc.

Inventor： Rotigni, Mario ,  Moseley, Richard ,  Bhatt, Piyush ,  Edgington, Gregory C.

IPC: H05K1/02

CPC classification number: H05K1/0231 ,  H05K1/0262 ,  H05K1/0298 ,  H05K2201/09309 ,  H05K2201/09327 ,  H05K2201/09336 ,  H05K2201/09345

Abstract: It is described a printed circuit board (50). The board comprises a first outer layer (23), a second outer layer (20) and an integrated circuit (2) mounted on the second outer layer. The integrated circuit has a single exposed pad (1) electrically connected to a ground reference, it has a first supply pin (5) electrically connected to a first power supply (VCC1) and it has a second supply pin (105) electrically connected to a second power supply, wherein the first power supply is configured to generate a first supply current with frequency components higher than the frequency components of a second supply current generated by the second power supply. The board further comprises a first decoupling capacitor (3) mounted on the second outer layer in the proximity of the first supply pin (5), the first decoupling capacitor having a first terminal (8) electrically connected with the first supply pin (5) and having a second terminal (9), it comprises an inner layer (21) interposed between the first outer layer (23) and the second outer layer (20), the inner layer comprising a metal layer (4) electrically connected to said ground reference, it comprises a first Via (7-1) configured to electrically connect the exposed pad (1) with the metal layer (4) of the inner layer, it comprises a second Via (6) configured to electrically connect the second terminal (9) of the first decoupling capacitor with the metal layer (4) of the inner layer and it comprises a second decoupling capacitor (173) having a first pin (278) electrically connected to the second power supply and having a second pin (279) electrically connected to said ground reference.

Abstract translation: 描述了印刷电路板（50）。 板包括安装在第二外层上的第一外层（23），第二外层（20）和集成电路（2）。 集成电路具有电连接到接地基准的单个裸露焊盘（1），其具有电连接到第一电源（VCC1）的第一电源引脚（5），并且其具有电连接到 第二电源，其中所述第一电源被配置为产生具有高于由所述第二电源产生的第二电源电流的频率分量的频率分量的第一电源电流。 该板还包括安装在第二外层附近的第一电源引脚（5）的第一去耦电容器（3），第一去耦电容器具有与第一电源引脚（5）电连接的第一端子（8） 并且具有第二端子（9），其包括介于所述第一外层（23）和所述第二外层（20）之间的内层（21），所述内层包括电连接到所述地面的金属层（4） 参考，它包括被配置为将暴露的焊盘（1）与内层的金属层（4）电连接的第一通孔（7-1），其包括构造成电连接第二端子的第二通孔（6） 第一去耦电容器与内层的金属层（4）的第二去耦电容器（173），并且其包括第二去耦电容器（173），其具有电连接到第二电源并具有第二引脚（279）的第一引脚（278） 电连接到所述接地基准。

公开(公告)号：EP1636838A2

公开(公告)日：2006-03-22

申请号：EP04754645.2

申请日：2004-06-03

Applicant: INTEL CORPORATION

Inventor： HESTER, Jennifer ,  LI, Yuan-Liang ,  DESMITH, Michael ,  FIGUEROA, David ,  ZHONG, Dong

IPC: H01L23/00

CPC classification number: H05K1/114 ,  H01G4/385 ,  H01L23/49838 ,  H01L23/642 ,  H01L2224/16 ,  H01L2224/16227 ,  H01L2924/00014 ,  H01L2924/01021 ,  H01L2924/01057 ,  H01L2924/15312 ,  H01L2924/19106 ,  H01L2924/3011 ,  H05K1/0231 ,  H05K2201/09263 ,  H05K2201/09345 ,  H05K2201/0979 ,  H05K2201/10636 ,  Y02P70/611 ,  H01L2224/0401

Abstract: According to some embodiments, a device includes a first conductive plane electrically coupled to a first terminal associated with a first polarity and a second terminal associated with the first polarity, a second conductive plane electrically coupled to a third terminal associated with a second polarity, a dielectric disposed between the first conductive plane and the second conductive plane, a third conductive plane electrically coupled to the second terminal and not electrically coupled to the first terminal, and a second dielectric disposed between the second conductive plane and the third conductive plane. A first capacitance is present between the first terminal and the third terminal, a second capacitance is present between the second terminal and the third terminal, and the first capacitance and the second capacitance may be substantially dissimilar.

公开(公告)号：EP2655959A2

公开(公告)日：2013-10-30

申请号：EP11805220.8

申请日：2011-12-09

Applicant: Koninklijke Philips N.V.

Inventor： CORNELISSEN, Hugo Johan ,  CENNINI, Giovanni ,  DEKKER, Tim

IPC: F21S8/00 ,  F21V7/00 ,  F21Y105/00

CPC classification number: F21V7/0083 ,  F21S8/00 ,  F21V7/00 ,  F21Y2105/10 ,  F21Y2115/10 ,  H05K1/162 ,  H05K1/189 ,  H05K3/10 ,  H05K2201/09345 ,  H05K2201/10106 ,  Y10T29/49155

Abstract: A lighting system comprises a circuit board which carries a lighting circuit comprising a plurality of lighting elements. The surface of the circuit board carrying the lighting elements is at least partially reflective. A spacer layer is over the circuit board and a top reflector is over the spacer layer. The spacer layer defines a light cavity air gap between the circuit board and the top reflector, and the top reflector and/or the circuit board is provided with an array of light out-coupling structures.

Abstract translation: 照明系统包括电路板（30），其承载包括多个照明元件（72）的照明电路。 承载照明元件的电路板（30）的表面至少是部分反射的。 间隔层（70）在电路板上方，顶部反射器（82）在间隔层上方。 间隔层限定了电路板和顶部反射器之间的光腔气隙，并且顶部反射器和/或电路板设置有一个出光耦合结构的阵列。

公开(公告)号：EP1455557A3

公开(公告)日：2006-01-04

申请号：EP03023937.0

申请日：2003-10-22

Applicant: ROBERT BOSCH GMBH

Inventor： Roozenbeck, Herman ,  Bayer, Uwe

IPC: H05K1/02

CPC classification number: H05K1/0216 ,  H05K1/0231 ,  H05K1/115 ,  H05K1/117 ,  H05K1/18 ,  H05K2201/0715 ,  H05K2201/09254 ,  H05K2201/09318 ,  H05K2201/09345 ,  H05K2201/09627 ,  H05K2201/10689

Abstract: Die vorliegende Erfindung stellt eine Trägervorrichtung (10) für elektrische Bauelemente bereit mit: einer ersten leitfähigen Ebene (23') zum Bereitstellen eines Bezugspotentials (23); und mindestens einer elektrisch von der ersten Ebene (23') isolierten zweiten Ebene (11') mit strukturierten Leitungen (11) zum Anbinden elektrischer Anschlusseinrichtungen (12) externer Bauelemente und zum Anbinden interner Bauelemente auf der Trägervorrichtung (10), wobei die Leitungen (11) zum Anbinden elektrischer Anschlusseinrichtungen (12) externer analoger Bauelemente und/oder Sensoren Bezugspotentialleitungen (16, 17) aufweisen, welche sich an einem ersten Stempunkt (18) sammeln, und die Leitungen (11) zum Anbinden interner Bauelemente Bezugspotentialleitungen (19, 20, 21) aufweisen, welche sich an einem zweiten Sternpunkt (22) sammeln und über mindestens eine Durchkontaktierungseinrichtung (23") mit der ersten Ebene (23') galvanisch gekoppelt sind und/oder die Durchkontaktierungseinrichtung (23") den ersten und/oder zweiten Stempunkt (18, 22) bildet.

公开(公告)号：EP3133906A4

公开(公告)日：2017-12-06

申请号：EP15779477

申请日：2015-04-09

Applicant: NIDEC SANKYO CORP

Inventor： GOMI KAZUHIRO ,  KURIBAYASHI IKURO

IPC: H05K1/02 ,  G06F21/86 ,  G06K7/00

CPC classification number: G06F21/86 ,  G06K7/00 ,  G06K7/087 ,  G06K7/10009 ,  H05K1/0219 ,  H05K1/0275 ,  H05K2201/09345

Abstract: Provided is a printed circuit board having a breakdown detection pattern formed thereon for preventing illicit acquisition of sensitive data, the printed circuit board being configured so that false detection of a disconnection or a short in the breakdown detection pattern can be prevented. The printed circuit board (7) comprises a breakdown detection pattern layer (32) wherein a breakdown detection pattern is formed for detecting a disconnection and/or a shorting thereof, a first pattern layer (31) disposed more to a Y1 direction side than the breakdown detection pattern layer (32), a second pattern layer (33) disposed more to a Y2 direction side than the breakdown detection pattern layer (32), and signal pattern layers (34 to 36) disposed more to the Y2 direction side than the second pattern layer (33). Formed in the first pattern layer (31) are a grounding pattern and a power source pattern covering the breakdown detection pattern from the Y1 direction side. Formed in the second pattern layer (33) are a grounding pattern and a power source pattern covering the breakdown detection pattern from the Y2 direction side.

公开(公告)号：EP0926930A3

公开(公告)日：2000-06-28

申请号：EP98309866.6

申请日：1998-12-02

Applicant: Hewlett-Packard Company

Inventor： Wharton, Robert J. ,  Daniel, Eric R. ,  Brown, Joseph D.

IPC: H05K1/11 ,  H05K1/02 ,  H05K13/08 ,  G01R31/28

CPC classification number: G01R31/316 ,  H05K1/0268 ,  H05K1/111 ,  H05K3/3436 ,  H05K13/08 ,  H05K2201/0761 ,  H05K2201/09345 ,  H05K2201/09772 ,  H05K2201/10106 ,  H05K2201/10734 ,  Y02P70/611

Abstract: A printed circuit board (10) has a first image (11). In the first image (11) there is a first ball grid array pattern (61) for attaching a first input/output ball grid array package. The first ball grid array pattern (61) includes a de-populated center area. A first surface insulation resistance pattern (62) is laid out within the de-populated center area of the first ball grid array pattern (61). A second ball grid array pattern (24) also may be contained within the first image (11). The second ball grid array pattern (24) is for attaching a second input/output ball grid array package. The second ball grid array pattern (24) has rows of interconnect pads (81). A second surface insulation resistance pattern (82) is laid out between the rows of interconnect pads (81).

公开(公告)号：EP3306792A1

公开(公告)日：2018-04-11

申请号：EP15894081.7

申请日：2015-05-29

Applicant: Shindengen Electric Manufacturing Co., Ltd.

Inventor： SASAKI, Mitsumasa

IPC: H02K11/00

CPC classification number: H05K1/0224 ,  H02K11/00 ,  H02K11/33 ,  H02P25/16 ,  H05K1/0203 ,  H05K1/181 ,  H05K5/0008 ,  H05K5/0026 ,  H05K2201/09027 ,  H05K2201/09063 ,  H05K2201/093 ,  H05K2201/09345 ,  H05K2201/09354 ,  H05K2201/1009 ,  H05K2201/10166 ,  H05K2201/10287 ,  H05K2201/1034 ,  H05K2201/10522

Abstract: A semiconductor device of the present invention includes: a substrate (12) that is annular or partially annular; a first phase control circuit (14) provided on the substrate (12), the first phase control circuit being configured to control a first phase of a plurality of phases of a motor; a second phase control circuit (15) provided on the substrate (12) so as to be adjacent to the first phase control circuit (14) in a circumferential direction of the substrate (12), the second phase control circuit (15) being configured to control a second phase of the plurality of phases of the motor, the second phase being different from the first phase; a power supply wiring (18) disposed on one of an outer circumferential side and an inner circumferential side of the first phase control circuit (14) and the second phase control circuit (15) in a radial direction of the substrate (12), the power supply wiring (18) being connected to the first phase control circuit (14) and the second phase control circuit (15), and the power supply wiring (18) extending in the circumferential direction of the substrate (12); and a ground winding (19) disposed on an other one of the outer circumferential side and the inner circumferential side of the first phase control circuit (14) and the second phase control circuit (15) in the radial direction of the substrate (12), the ground winding (19) being connected to the first phase control circuit (14) and the second phase control circuit (15), and the ground winding (19) extending in the circumferential direction of the substrate (12).

Abstract translation: 本发明的半导体器件包括：基板（12），其为环形或部分环形; 设置在所述基板（12）上的第一相位控制电路（14），所述第一相位控制电路被配置为控制电动机的多个相的第一相; 第二相位控制电路（15），其设置在所述基板（12）上，以便在所述基板（12）的圆周方向上与所述第一相位控制电路（14）相邻;所述第二相位控制电路 以控制所述电动机的所述多个相的第二相，所述第二相与所述第一相不同; 在所述第一相位控制电路（14）和所述第二相位控制电路（15）的所述基板（12）的半径方向的外周侧和内周侧中的一方设置的电源布线（18），所述 电源布线（18）连接到第一相位控制电路（14）和第二相位控制电路（15），电源布线（18）沿基板（12）的圆周方向延伸。 以及设置在所述第一相位控制电路（14）和所述第二相位控制电路（15）的所述基板（12）的径向外周侧和内周侧中的另一方上的接地绕组（19） ，接地绕组（19）连接到第一相位控制电路（14）和第二相位控制电路（15），接地绕组（19）沿基板（12）的圆周方向延伸。

公开(公告)号：EP3133906A1

公开(公告)日：2017-02-22

申请号：EP15779477.7

申请日：2015-04-09

Applicant: Nidec Sankyo Corporation

Inventor： GOMI, Kazuhiro ,  KURIBAYASHI, Ikuro

IPC: H05K3/46 ,  G06F21/86 ,  G06K7/00

CPC classification number: G06F21/86 ,  G06K7/00 ,  G06K7/087 ,  G06K7/10009 ,  H05K1/0219 ,  H05K1/0275 ,  H05K2201/09345

Abstract: Provided is a printed circuit board having a breakdown detection pattern formed thereon for preventing illicit acquisition of sensitive data, the printed circuit board being configured so that false detection of a disconnection or a short in the breakdown detection pattern can be prevented. The printed circuit board (7) comprises a breakdown detection pattern layer (32) wherein a breakdown detection pattern is formed for detecting a disconnection and/or a shorting thereof, a first pattern layer (31) disposed more to a Y1 direction side than the breakdown detection pattern layer (32), a second pattern layer (33) disposed more to a Y2 direction side than the breakdown detection pattern layer (32), and signal pattern layers (34 to 36) disposed more to the Y2 direction side than the second pattern layer (33). Formed in the first pattern layer (31) are a grounding pattern and a power source pattern covering the breakdown detection pattern from the Y1 direction side. Formed in the second pattern layer (33) are a grounding pattern and a power source pattern covering the breakdown detection pattern from the Y2 direction side.

Abstract translation: 提供了一种印刷电路板，其上形成有用于防止非法获取敏感数据的击穿检测图案，印刷电路板被配置为可以防止故障检测图案的断线或短路错误检测。 印刷电路板（7）包括击穿检测图案层（32），其中形成用于检测断开和/或短路的击穿检测图案，第一图案层（31）比Y1方向侧更多地设置 击穿检测图案层（32），比击穿检测图案层（32）更多地设置在Y2方向侧的第二图案层（33）以及比Y2方向侧更多配置的信号图案层（34〜36） 第二图案层（33）。 形成在第一图案层（31）中的是从Y1方向侧覆盖击穿检测图案的接地图案和电源图案。 形成在第二图案层（33）中的是从Y2方向侧覆盖击穿检测图案的接地图案和电源图案。