公开(公告)号：EP2085816A1

公开(公告)日：2009-08-05

申请号：EP09000967.1

申请日：2009-01-23

Applicant: FCM Co., Ltd.

Inventor： Miura, Shigeki

IPC: G02F1/1345 ,  H01L23/532 ,  H01L27/32

CPC classification number: G02F1/1345 ,  G02F2001/13629 ,  H01L27/3279 ,  H01L27/329 ,  H01L2251/308 ,  H05K3/24 ,  H05K2201/0108 ,  H05K2201/0326 ,  H05K2201/0338

Abstract: An electrode substrate (100) of the present invention includes a first conductive layer (102) made of a first conductive material and a second conductive layer (103) made of a second conductive material formed on a transparent base material (101), wherein the first conductive layer (102) is formed on the transparent base material (101), the second conductive layer (103) is formed on the transparent base material (101) to cover the first conductive layer (102), both the first conductive layer (102) and the second conductive layer (103) form a fine wiring pattern, the second conductive layer (103) has a width (W 2 ) not less than 1.5 times and not more than 300 times that (W 1 ) of the first conductive layer (102), and the second conductive material has a light transmissivity higher than that of the first conductive material, and a conductivity lower than that of the first conductive material.

Abstract translation: 本发明的电极基板（100）包括由形成在透明基体材料（101）的第二导电材料制成的第一导电材料和第二导电层（103）的第一导电层（102）的worin （第一导电层（102）在透明基体材料（101），第二导电层（103）形成的形成在透明基体材料（101）以覆盖所述第一导电层（102）两者的第一导电层 102）和第二导电层（103）形成微细的配线图案，所述第二导电层（103）的宽度（W 2）不小于1.5倍但不超过300倍那样（W 1）的第一导电 层（102）和所述第二导电材料具有的光透射率比所述第一导电材料的高，并且比所述第一导电材料的低的电导率。

公开(公告)号：EP2076103A2

公开(公告)日：2009-07-01

申请号：EP08009524.3

申请日：2008-05-23

Applicant: LG Electronics Inc.

Inventor： Lee, Sang Gon ,  Kim, Dae Sung ,  Chang, Woo Hyuck

IPC: H05K1/14 ,  H05K3/24

CPC classification number: H05K3/388 ,  H01L2224/16225 ,  H01L2924/12044 ,  H05K1/028 ,  H05K1/147 ,  H05K1/189 ,  H05K3/243 ,  H05K2201/0191 ,  H05K2201/0338 ,  H05K2201/10128 ,  H05K2201/10681 ,  Y10T428/12389 ,  Y10T428/24917 ,  Y10T428/2495 ,  H01L2924/00

Abstract: A flexible film (210) is provided. The flexible film includes a dielectric film (212); and a metal layer (214) disposed on the dielectric film, wherein the ratio of the thickness of the metal layer to the thickness of the dielectric film is about 1:3 to 1:10. Therefore, it is possible to improve the peel strength, dimension stability, and tensile strength of a flexible film by limiting the ratio of the thicknesses of a dielectric film and a metal layer of the flexible film.

Abstract translation: 提供柔性膜（210）。 该柔性膜包括电介质膜（212）; 和设置在所述电介质膜上的金属层（214），其中所述金属层的厚度与所述电介质膜的厚度之比为约1：3至1:10。 因此，通过限制柔性膜的电介质膜和金属层的厚度比率，可以改善柔性膜的剥离强度，尺寸稳定性和拉伸强度。

公开(公告)号：EP1956114A1

公开(公告)日：2008-08-13

申请号：EP07090013.9

申请日：2007-01-30

Applicant: ATOTECH Deutschland GmbH

Inventor： Hirsekorn, Isabel-Roda ,  Rossenbeck, Britta, Dr. ,  Schreier, Hans-Jürgen, Dr. ,  Sebald, Christian ,  Wegricht, Jens ,  Beck, Thomas ,  Kuldip, Singh Johal

IPC: C23C18/31 ,  C23C18/42 ,  H05K3/24

CPC classification number: H05K3/244 ,  C23C18/1651 ,  C23C18/32 ,  C23C18/44 ,  C23C18/54 ,  H01L24/11 ,  H01L2224/0554 ,  H01L2224/05567 ,  H01L2224/05573 ,  H01L2224/05647 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/351 ,  H05K3/3463 ,  H05K2201/0338 ,  H05K2203/072 ,  H05K2203/073 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: To achieve good solder performance with Pd-free solder to a BGA design, a layer assembly comprising first, second and, optionally, third sub-layers is provided, wherein said first sub-layer comprises a first material, said first material comprising nickel and phosphorus and said first sub-layer being in contact with said second sub-layer; said second sub-layer comprises a second material, said second material comprising palladium and phosphorus and said second sub-layer being in contact with said first sub-layer and said third sub-layer and wherein said second sub-layer is at least 0.1 µm thick; and said third sub-layer comprises a third material, said third material consisting of gold or a gold alloy and said third sub-layer being in contact with said second sub-layer. Such layer assembly is coated to the copper structure which is provided on one or on both sides of the carrier corpus of a circuit carrier.

Abstract translation: 为了实现用Pd-无铅焊料到BGA设计中，层组件包括第一，第二和任选的第三子层良好的焊料性能设置，worin所述第一子层包括第一材料，所述第一材料包含镍和 磷和所述第一子层与所述第二子层接触; 所述第二子层包括第二材料，所述第二材料包括钯，磷和所述第二子层具有与所述第一子层接触和所述第三子层和worin所述第二子层为至少0.1微米 厚; 和所述第三子层包括第三材料，所述第三材料由金或金合金，并且所述第三子层与所述第二子层接触。 搜索层组件被涂覆到铜结构中的所有其设置在一个或上的电路载波的载波语料库的bothsides。

公开(公告)号：EP1893006A1

公开(公告)日：2008-02-27

申请号：EP07108839.7

申请日：1999-09-28

Applicant: IBIDEN CO., LTD.

Inventor： En, Honchin ,  Hayashi, Masayuki ,  Wang, Dongdong ,  Shimada, Kenichi ,  Asai, Motoo ,  Sekine, Koji ,  Nakai, Tohru ,  Ichikawa, Shinichiro ,  Toyoda, Yukihiko

IPC: H05K3/46 ,  C23G1/10

CPC classification number: C23G1/10 ,  H01L2924/0002 ,  H05K3/0094 ,  H05K3/062 ,  H05K3/067 ,  H05K3/108 ,  H05K3/384 ,  H05K3/385 ,  H05K3/388 ,  H05K3/4602 ,  H05K3/4644 ,  H05K3/4661 ,  H05K2201/0129 ,  H05K2201/0158 ,  H05K2201/0338 ,  H05K2201/09563 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2203/0307 ,  H05K2203/0315 ,  H05K2203/072 ,  H05K2203/1105 ,  Y10T29/49124 ,  Y10T29/49151 ,  Y10T29/49155 ,  Y10T29/49163 ,  Y10T29/49165 ,  Y10T428/24917 ,  H01L2924/00

Abstract: A multilayer printed circuit board comprises a substrate board (101) carrying a lower-layer conductor circuit (104) and, as built up on the substrate board (101) successively and alternately, an interlayer resin insulating layer (102) and an upper-layer conductor circuit (105) in succession. The multilayer printed circuit board further comprises a metal layer (111a) composed of at least one metal selected from among metals having ionization tendencies not lower than tin but not higher than aluminum and noble metals as formed on the surface of said lower-layer conductor circuit (104) and a roughened layer (111b) superimposed on said metal layer (111a).

Abstract translation: 多层印刷电路板包括承载下层导体电路（104）的衬底板（101），并且在衬底板（101）上依次并且交替地形成层间树脂绝缘层（102）和上层导体电路 层导体电路（105）。 多层印刷电路板还包括金属层（111a），其由从具有不低于锡但不高于铝的电离趋势的金属中选择的至少一种金属和在所述下层导体电路的表面上形成的贵金属 （104）和叠加在所述金属层（111a）上的粗糙层（111b）。

公开(公告)号：EP1830616A2

公开(公告)日：2007-09-05

申请号：EP07110630.6

申请日：1999-09-28

Applicant: IBIDEN CO., LTD.

Inventor： En, Honchin ,  Hayashi, Masayuki ,  Wang Dongdong ,  Shimada, Kenichi ,  Asai, Motoo ,  Sekine, Koji ,  Nakai, Tohru ,  Ichikawa, Shinichiro ,  Toyoda, Yukihiko

IPC: H05K3/46

CPC classification number: C23G1/10 ,  H01L2924/0002 ,  H05K3/0094 ,  H05K3/062 ,  H05K3/067 ,  H05K3/108 ,  H05K3/384 ,  H05K3/385 ,  H05K3/388 ,  H05K3/4602 ,  H05K3/4644 ,  H05K3/4661 ,  H05K2201/0129 ,  H05K2201/0158 ,  H05K2201/0338 ,  H05K2201/09563 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2203/0307 ,  H05K2203/0315 ,  H05K2203/072 ,  H05K2203/1105 ,  Y10T29/49124 ,  Y10T29/49151 ,  Y10T29/49155 ,  Y10T29/49163 ,  Y10T29/49165 ,  Y10T428/24917 ,  H01L2924/00

Abstract: In a process for manufacturing a multilayer printed circuit board which comprises forming a resin insulating layer (12) and a conductor circuit (19) on a resin substrate (1), a metal layer (14) composed of at least one metal selected from among the metal elements of the 4 th through 7 th periods in Group 4A through Group 1B of the long-form periodic table of the elements, A1 and Sn is formed on the surface of the resin insulating layer (12), the surface of the metal layer (14) is then cleaned with an acid, and thereafter the conductor circuit (19) is constructed on the metal layer (14).

Abstract translation: 在制造多层印刷电路板的方法中，包括在树脂基板（1）上形成树脂绝缘层（12）和导体电路（19），金属层（14）由至少一种选自 在树脂绝缘层（12）的表面上形成元件A1和Sn的长型周期表的第4A至1B组中的第4至第7周期的金属元素，金属表面 然后用酸清洗层（14），之后将导体电路（19）构造在金属层（14）上。

公开(公告)号：EP1601821A4

公开(公告)日：2007-03-14

申请号：EP04718225

申请日：2004-03-08

Applicant: MICRO RELAY HOLDINGS PTY LTD

Inventor： SEXTON BRETT ,  DAVIS THIMOTHY J

IPC: B81B3/00 ,  B81C1/00 ,  C25D5/12 ,  H05K3/40

CPC classification number: B81C1/00666 ,  B81B2201/018 ,  B81B2203/0118 ,  B81C2201/0167 ,  C25D5/12 ,  H01H2059/0081 ,  H05K3/4092 ,  H05K2201/0311 ,  H05K2201/0338 ,  H05K2201/0397 ,  H05K2203/0726

Abstract: Curved out of plane metal components are formed on PCB substrates (11) by electroplating two layers (13, 14) of the same metal such that each layer has a different internal stress. This produces as curvature of the layer (13, 14) which enables coils, curved cantilever beams and springs to be fabricated. The amplitude and direction of curvature can be controlled by controlling the stress and thickness of each layer. The stress is controlled by controlling the composition of the electroplating bath.

公开(公告)号：EP1727409A1

公开(公告)日：2006-11-29

申请号：EP06115377.1

申请日：1999-09-28

Applicant: IBIDEN CO., LTD.

Inventor： En, Honchin ,  Hayashi, Masayuki ,  Wang, Dongdong ,  Shimada, Kenichi ,  Asai, Motoo ,  Sekine, Koji ,  Nakai, Tohru ,  Ichikawa, Shinichiro ,  Toyoda, Yukihiko

IPC: H05K3/46 ,  H05K3/38

CPC classification number: C23G1/10 ,  H01L2924/0002 ,  H05K3/0094 ,  H05K3/062 ,  H05K3/067 ,  H05K3/108 ,  H05K3/384 ,  H05K3/385 ,  H05K3/388 ,  H05K3/4602 ,  H05K3/4644 ,  H05K3/4661 ,  H05K2201/0129 ,  H05K2201/0158 ,  H05K2201/0338 ,  H05K2201/09563 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2203/0307 ,  H05K2203/0315 ,  H05K2203/072 ,  H05K2203/1105 ,  Y10T29/49124 ,  Y10T29/49151 ,  Y10T29/49155 ,  Y10T29/49163 ,  Y10T29/49165 ,  Y10T428/24917 ,  H01L2924/00

Abstract: In a process for manufacturing a multilayer printed circuit board which comprises constructing a conductor circuit (104), roughening the conductor circuit (104) to provide a roughened surface (111), forming an interlayer resin insulating layer (102) over the roughened surface (111) of the conductor circuit (104) and forming openings (106) for via holes in a repeated sequence to construct conductor circuits comprised a plurality of layers isolated by interlayer resin insulating layers, an oxidation treatment is carried out after forming the roughened surface (111) on the conductor circuit (104) to provide an oxide film on the entire roughened surface (111), and thereafter the interlayer resin insulating layer (102) is constructed.

Abstract translation: 在制造多层印刷电路板的方法中，包括构造导体电路（104），粗化导体电路（104）以提供粗糙化表面（111），在粗糙表面上形成层间树脂绝缘层（102） 111），并且以重复的顺序形成用于通孔的开口（106），以构成包括由层间树脂绝缘层隔离的多个层的导体电路，在形成粗糙表面之后进行氧化处理（ 111），在整个粗糙面（111）上形成氧化膜，之后构成层间树脂绝缘层（102）。

公开(公告)号：EP1280213A3

公开(公告)日：2006-10-11

申请号：EP02016496.8

申请日：2002-07-23

Applicant: Pioneer Corporation

Inventor： Nagayama, Kenichi, Corporate Research and ,  Sugimoto, Akira, Corporate Research and ,  Miyaguchi, Satoshi, Corporate Research and

IPC: H01L51/20 ,  H01B1/02

CPC classification number: H05K3/061 ,  H01L27/329 ,  H01L51/5212 ,  H01L2924/0002 ,  H05K1/09 ,  H05K3/062 ,  H05K2201/0338 ,  H05K2203/0577 ,  H05K2203/1184 ,  H01L2924/00

Abstract: A layered wiring line of silver or silver alloy includes a silver or silver alloy conductor layer (32) including silver or silver alloy; and a protective conductor layer (31) layered on and covering the silver or silver alloy conductor layer. A method for forming the layered wiring line includes steps of: layering the silver or silver alloy conductor layer and the protective conductor layer on a substrate in turn; making the protective conductor layer in contact with a liquid etchant common to the silver or silver alloy conductor layer and the protective conductor layer by a predetermined pattern. The protective conductor layer has a thickness satisfying a relationship in that a ratio of (the protective conductor layer's thickness) / (the silver or silver alloy conductor layer's thickness) is less than that of (a solution velocity of the protective conductor layer in the liquid etchant) / (a solution velocity of the silver or silver alloy conductor layer in the liquid etchant).

公开(公告)号：EP1601821A1

公开(公告)日：2005-12-07

申请号：EP04718225.8

申请日：2004-03-08

Applicant: Micro Relay Holdings Pty Ltd

Inventor： SEXTON, Brett,CSIRO ,  DAVIS, Thimothy J.,CSIRO

IPC: C25D5/12

CPC classification number: B81C1/00666 ,  B81B2201/018 ,  B81B2203/0118 ,  B81C2201/0167 ,  C25D5/12 ,  H01H2059/0081 ,  H05K3/4092 ,  H05K2201/0311 ,  H05K2201/0338 ,  H05K2201/0397 ,  H05K2203/0726

Abstract: Curved out of plane metal components are formed on PCB substrates (11) by electroplating two layers (13, 14) of the same metal such that each layer has a different internal stress. This produces as curvature of the layer (13, 14) which enables coils, curved cantilever beams and springs to be fabricated. The amplitude and direction of curvature can be controlled by controlling the stress and thickness of each layer. The stress is controlled by controlling the composition of the electroplating bath.

公开(公告)号：EP1534510A2

公开(公告)日：2005-06-01

申请号：EP03760348.7

申请日：2003-06-12

Applicant: AVERY DENNISON CORPORATION

Inventor： HE, Xiao-Ming ,  HEYDARPOUR, Ramin

IPC: B32B9/04

CPC classification number: C23C14/562 ,  B29D11/0073 ,  C23C14/022 ,  C23C14/08 ,  C23C14/205 ,  G02F1/133305 ,  G02F1/13439 ,  H01B1/02 ,  H01B1/08 ,  H05K1/0393 ,  H05K3/381 ,  H05K2201/0338 ,  H05K2203/095 ,  H05K2203/1545 ,  Y10T428/31504

Abstract: Methods for roll-to-roll deposition of optically transparent and high conductivity metallic thin films are disclosed. In general, a method according to the present invention comprises: (1) providing a flexible plastic substrate; (2) depositing a multi-layered conductive metallic film on the flexible plastic substrate by a thin-film deposition technique to form a composite film; and (3) collecting the composite film in continuous rolls. Typically, the thin conductive metallic film is an InCeO-Ag-InCeO film. Typically, the thin-film deposition technique is DC magnetron sputtering. Another aspect of the invention is a composite film produced by a method according to the present invention. Still another aspect of the invention is a composite film comprising InCeO-Ag-InCeO film formed on a flexible plastic substrate, wherein the composite fillm has a combination of properties including: transmittance of at least 90% throughout the visible region; an electrical resistance of no greater than about 10 ohm/square; a root-mean-square roughness of no greater than about 2.5 nm; and an interlayer adhesion between the InCeO/Ag/InCeO metallic film and the remainder of the composite film that is sufficiently great to survive a 180° peel adhesion test.