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    A system of functional units for performing logic functions
    83.
    发明公开
    A system of functional units for performing logic functions 失效
    系统funktioneller Einheiten zurDurchführunglogischer Funktionen。

    公开(公告)号：EP0023972A2

    公开(公告)日：1981-02-18

    申请号：EP80103967.8

    申请日：1980-07-10

    申请人： International Business Machines Corporation

    发明人： Das Gupta, Sumit ,  Goel, Prabhakar ,  Williams, Thomas Walter

    IPC分类号： G06F11/26

    CPC分类号： G01R31/318541 ,  G01R31/318583

    摘要： According to the invention, the LSI testing methods allow the states of combinational logic networks to be captured in either a group of master latches (390) or slave latches (400) of shift registers used for performing scan-in scan-out operations on test data (test patterns, result patterns), but not both.
    If on a particular test the states are captured in the master latches, then each master latch state is subsequently shifted to the corresponding slave latch by the application of a shift clock, as known from the art.
    If instead the states are captured in the slave latches the slave latches can be immediately shifted out for inspection.

    摘要翻译： 根据本发明，LSI测试方法允许组合逻辑网络的状态被捕获在用于执行扫描/扫描输出操作的移位寄存器的一组主锁存器（390）或从锁存器（400）中 测试数据（测试模式，结果模式），但不能同时复位，如果在特定测试中，状态被捕获在主锁存器中，则每个主锁存状态随后通过应用 如本领域已知的移位时钟。 ... 如果在从锁存器中捕获状态，则可以将从动锁存器立即移出来进行检查。

    EFFECTIVE SCAN COVERAGE
    84.
    发明公开
    EFFECTIVE SCAN COVERAGE 审中-公开

    公开(公告)号：EP4407327A1

    公开(公告)日：2024-07-31

    申请号：EP24150870.4

    申请日：2024-01-09

    申请人： STMicroelectronics International N.V.

    发明人： SRINIVASAN, V Narayanan ,  SRIVASTAVA, Umesh Chandra ,  VATS, Shiv Kumar ,  SHARMA, Manish

    IPC分类号： G01R31/3185

    CPC分类号： G01R31/318544 ,  G01R31/318541 ,  G01R31/318536

    摘要： According to an embodiment, a digital circuit (400) includes an OR gate (402) and a flip-flop (406). The OR gate (402) includes a first input and a second input. The first input of the OR gate is coupled to a control signal (CTRL), and the second input of the OR gate is coupled to an uncovered functional combination logic of the digital circuit (400). The first input of the OR gate (402) is configured to be pulled low by the control signal (CTRL) in response to setting the digital circuit (400) in a configuration to test the uncovered functional combination logic. The flip-flop (406) includes a reset pin (R) or a set pin (S) coupled to the output of the OR gate (402). The output of the flip-flop (406) is configured to be observed during a testing of the uncovered functional combination logic to detect defects in the digital circuit (400).

    SEMICONDUCTOR STORAGE DEVICE FOR SCAN CHAIN HAVING SYNCHRONOUS AND ASYNCHRONOUS MODES
    86.
    发明公开
    SEMICONDUCTOR STORAGE DEVICE FOR SCAN CHAIN HAVING SYNCHRONOUS AND ASYNCHRONOUS MODES 审中-公开
    HALBLEITERSPEICHERVORRICHTUNGFÜRABTASTKETTE MIT SYNCHRONEN UND ASYNCHRONEN MODI

    公开(公告)号：EP3065136A1

    公开(公告)日：2016-09-07

    申请号：EP16158204.4

    申请日：2016-03-02

    申请人： Freescale Semiconductor, Inc.

    发明人： CORSO, Jorge ,  BARROS, Marcos C. ,  LUJAN, Alexandre S.

    IPC分类号： G11C29/32 ,  G01R31/3185

    CPC分类号： G01R31/3177 ,  G01R31/318541 ,  G01R31/318575 ,  G01R31/318594 ,  G11C29/32

    摘要： A method for performing scan testing using a scan chain having a plurality of storage elements is described. During a capture phase, each storage element of the scan chain stores data from a first data input of the storage element synchronously to a clock signal. And during a shift phase, a scan pattern is shifted into the scan chain in which each storage element stores data from a second data input of the storage element asynchronously with the clock signal.

    摘要翻译： 描述使用具有多个存储元件的扫描链执行扫描测试的方法。 在捕获阶段，扫描链的每个存储元件与来自存储元件的第一数据输入的数据同时地存储到时钟信号。 并且在移位阶段期间，将扫描图案移入扫描链，其中每个存储元件与来自存储元件的第二数据输入的数据与时钟信号异步地存储。

    DISPOSITIF DE TEST ET DE SURVEILLANCE OU MONITORING DE CIRCUITS NUMERIQUES
    88.
    发明公开
    DISPOSITIF DE TEST ET DE SURVEILLANCE OU MONITORING DE CIRCUITS NUMERIQUES 有权
    VORRICHTUNG ZUMPRÜFENUNDÜBERWACHENDIGITALER SCHALTUNGEN

    公开(公告)号：EP2852846A1

    公开(公告)日：2015-04-01

    申请号：EP13709225.0

    申请日：2013-03-15

    申请人： Commissariat à l'Énergie Atomique et aux Énergies Alternatives

    发明人： GHERMAN, Valentin

    IPC分类号： G01R31/3185

    CPC分类号： G01R31/3177 ,  G01R31/31703 ,  G01R31/31725 ,  G01R31/31816 ,  G01R31/318541 ,  G01R31/318594

    摘要： The invention relates to a device for testing and monitoring digital circuits in order to detect delay errors affecting a signal D received directly at the input of a toggle called primary sampling member (100, 200), providing a first value D
    1 of the signal D and receiving a first clock signal (105a), said device comprising at least: a scan logic module (120) having a first input for receiving the signal "D", a second input for receiving a signal "scan in", and a third input for receiving a signal "scan enable" (103) suitable for selecting the operation mode of the test device in a scan or functional mode, an output (120s) connected to a secondary sampling member (110) providing a second sampled signal D
    2 of the signal D after passing through the scan logic module and receiving a second clock signal (105b), and a comparison module (150) for comparing the signal D
    1 and the signal D
    2 and generating an alert or error signal.

    摘要翻译： 一种用于检测和监视数字电路的装置，用于检测影响直接在称为主要采样元件的触发器的输入端的信号D的定时故障，提供信号D的第一值D1并接收第一时钟信号，至少包括 ：具有接收信号“D”的第一输入的扫描逻辑模块，接收“扫入”信号的第二输入端和接收适于在扫描中选择测试装置的操作模式的“扫描使能”信号的第三输入端 模式或操作模式，以及连接到二次采样元件的输出，其在通过扫描逻辑模块之后提供信号D的第二采样信号D2，并且接收第二时钟信号; 用于比较信号D1和产生报警或误差信号的信号D2的模块。