TRENCH MOS SCHOTTKY DIODE
    4.
    发明公开

    公开(公告)号:EP3588580A1

    公开(公告)日:2020-01-01

    申请号:EP18757087.4

    申请日:2018-02-27

    摘要: One embodiment of the present invention provides a trench MOS Schottky diode 1 which is provided with: a first semiconductor layer 10 which is formed from a Ga 2 O 3 single crystal; a second semiconductor layer 11 which is laminated on the first semiconductor layer 10 and has a trench 12 that opens to a surface 17, while being formed from a Ga 2 O 3 single crystal; an anode electrode 13 which is formed on the surface 17; a cathode electrode 14 which is formed on a surface of the first semiconductor layer 10, said surface being on the reverse side of the second semiconductor layer 11-side surface; an insulating film 15 which covers the inner surface of the trench 12 of the second semiconductor layer 11; and a trench MOS gate 16 which is buried within the trench 12 of the second semiconductor layer 11 so as to be covered by the insulating film 15, while being in contact with the anode electrode 13. The second semiconductor layer 11 is configured from: a lower layer 11b which is on the first semiconductor layer side; and an upper layer 11a which is on the anode electrode 13 side, while having a higher donor concentration than the lower layer 11b.

    TRENCH MOS-TYPE SCHOTTKY DIODE
    5.
    发明公开

    公开(公告)号:EP3451388A1

    公开(公告)日:2019-03-06

    申请号:EP17789388.0

    申请日:2017-04-20

    摘要: [Problem] To provide a trench MOS-type Schottky diode having a high withstand voltage and low loss. [Solution] According to one embodiment of the present invention, a trench MOS-type Schottky diode 1 is provided, said trench MOS-type Schottky diode having: a first semiconductor layer 10 formed of a Ga 2 O 3 single crystal; a second semiconductor layer 11, which is a layer laminated on the first semiconductor layer 10, and which has a trench 12 opened in a surface 17, said second semiconductor layer being formed of a Ga 2 O 3 single crystal; an anode electrode 13 formed on the surface 17; a cathode electrode 14 formed on the first semiconductor layer 10 surface on the reverse side of the second semiconductor layer 11; and an insulating film 15 covering the inner surface of the trench 12 of the second semiconductor layer 11; and a trench MOS gate 16, which is embedded in the trench 12 of the second semiconductor layer 11 such that the trench MOS gate is covered with the insulating film 15, and which is in contact with the anode electrode 13.

    TRENCH MOS-TYPE SCHOTTKY DIODE
    6.
    发明公开

    公开(公告)号:EP4086974A1

    公开(公告)日:2022-11-09

    申请号:EP22176745.2

    申请日:2017-04-20

    摘要: A trench MOS-type Schottky diode (1), comprising:
    a first semiconductor layer (10) comprising an n-type Ga 2 O 3 -based single crystal containing a Group IV element as a donor;
    a second semiconductor layer (11), comprising an n-type Ga 2 O 3 -based single crystal containing a Group IV element as a donor, laminated on the first semiconductor layer (10) and having trenches (12) opened on a surface (17) thereof opposite to the first semiconductor layer (10);
    an anode electrode (13) formed on the surface (17) of the second semiconductor layer (11) opposite to the first semiconductor layer (10) and being in Schottky contact with the second semiconductor layer (11);
    a cathode electrode (14) formed on a surface of the first semiconductor layer (10) opposite to the second semiconductor layer (11) and being in ohmic contact with the first semiconductor layer (10);
    an insulating films (15) covering inner surfaces of the trenches (12) of the second semiconductor layer (11); and
    a trench MOS gates (16) embedded in the trenches (12) of the second semiconductor layer (11) so as to be covered with the insulating films (15) and is in contact with the anode electrode (13),
    wherein a donor concentration in the second semiconductor layer (11) is lower than the donor concentration in the first semiconductor layer (10),
    wherein the donor concentration in the second semiconductor layer (11) is not less than 1.0×10 16 cm -3 and not more than 6.0×10 16 cm -3 , and
    wherein a thickness of the second semiconductor layer (11) is not less than 4.5 µm and not more than 9 µm.