公开(公告)号：EP2693474A2

公开(公告)日：2014-02-05

申请号：EP13177989.4

申请日：2013-07-25

申请人： IXYS CORPORATION

发明人： Zommer, Nathan

IPC分类号： H01L23/485 ,  H01L23/495 ,  H01L23/498

CPC分类号： H01L23/48 ,  H01L23/3735 ,  H01L23/4827 ,  H01L23/49513 ,  H01L23/49524 ,  H01L23/49562 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/40 ,  H01L24/48 ,  H01L24/49 ,  H01L24/72 ,  H01L24/73 ,  H01L24/80 ,  H01L24/84 ,  H01L24/85 ,  H01L24/92 ,  H01L24/95 ,  H01L2224/03312 ,  H01L2224/0345 ,  H01L2224/035 ,  H01L2224/03505 ,  H01L2224/0381 ,  H01L2224/04026 ,  H01L2224/04034 ,  H01L2224/04042 ,  H01L2224/05073 ,  H01L2224/05076 ,  H01L2224/05083 ,  H01L2224/05124 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05187 ,  H01L2224/05553 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05687 ,  H01L2224/05794 ,  H01L2224/05839 ,  H01L2224/0589 ,  H01L2224/0603 ,  H01L2224/06505 ,  H01L2224/08238 ,  H01L2224/4007 ,  H01L2224/40225 ,  H01L2224/40247 ,  H01L2224/40475 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48463 ,  H01L2224/48472 ,  H01L2224/4903 ,  H01L2224/4911 ,  H01L2224/73221 ,  H01L2224/73251 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/80439 ,  H01L2224/80895 ,  H01L2224/84205 ,  H01L2224/84424 ,  H01L2224/84801 ,  H01L2224/85181 ,  H01L2224/85205 ,  H01L2224/85424 ,  H01L2224/92 ,  H01L2224/92157 ,  H01L2224/9222 ,  H01L2224/92246 ,  H01L2224/92247 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/05432 ,  H01L2224/05139 ,  H01L2924/00015 ,  H01L2224/80 ,  H01L2224/84 ,  H01L2224/85 ,  H01L2224/08 ,  H01L2224/40 ,  H01L2224/48 ,  H01L2224/03 ,  H01L2924/207 ,  H01L2224/37099

摘要： A method of manufacturing a semiconductor die, comprising the steps of: (a) forming a plurality of separate amounts of silver nanoparticle paste on a top- side of a wafer (26) such that there is an amount of silver nanoparticle paste on a first aluminum pad (28) and such that there is no silver nanoparticle paste (29) on a second aluminum pad (27); and (b) sintering the amount of silver nanoparticle paste so that the amount of silver nanoparticle paste becomes a sintered silver structure disposed on the first aluminum pad (28) and so that the second aluminum pad (27) is not covered by any sintered silver layer.

摘要翻译： （a）在晶片（26）检测的顶侧形成的银纳米粒子膏的单独量的多元化thatthere是银纳米粒子膏的量上的第一：制造半导体其中，包括以下步骤的方法 铝垫（28）和这样thatthere没有银纳米粒子膏（29）上的第二铝焊盘（27）; 和（b）烧结的银纳米粒子膏的量，从而没有银纳米粒子膏的量变得设置在所述第一铝垫（28）的烧结银结构，所以没有第二铝垫（27）未包括的任何烧结银 层。

公开(公告)号：EP2693474A3

公开(公告)日：2014-10-08

申请号：EP13177989.4

申请日：2013-07-25

申请人： IXYS CORPORATION

发明人： Zommer, Nathan

IPC分类号： H01L23/485 ,  H01L23/49 ,  H01L23/488 ,  H01L21/60 ,  H01L23/373 ,  H01L23/495

CPC分类号： H01L23/48 ,  H01L23/3735 ,  H01L23/4827 ,  H01L23/49513 ,  H01L23/49524 ,  H01L23/49562 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/40 ,  H01L24/48 ,  H01L24/49 ,  H01L24/72 ,  H01L24/73 ,  H01L24/80 ,  H01L24/84 ,  H01L24/85 ,  H01L24/92 ,  H01L24/95 ,  H01L2224/03312 ,  H01L2224/0345 ,  H01L2224/035 ,  H01L2224/03505 ,  H01L2224/0381 ,  H01L2224/04026 ,  H01L2224/04034 ,  H01L2224/04042 ,  H01L2224/05073 ,  H01L2224/05076 ,  H01L2224/05083 ,  H01L2224/05124 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05187 ,  H01L2224/05553 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05687 ,  H01L2224/05794 ,  H01L2224/05839 ,  H01L2224/0589 ,  H01L2224/0603 ,  H01L2224/06505 ,  H01L2224/08238 ,  H01L2224/4007 ,  H01L2224/40225 ,  H01L2224/40247 ,  H01L2224/40475 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48463 ,  H01L2224/48472 ,  H01L2224/4903 ,  H01L2224/4911 ,  H01L2224/73221 ,  H01L2224/73251 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/80439 ,  H01L2224/80895 ,  H01L2224/84205 ,  H01L2224/84424 ,  H01L2224/84801 ,  H01L2224/85181 ,  H01L2224/85205 ,  H01L2224/85424 ,  H01L2224/92 ,  H01L2224/92157 ,  H01L2224/9222 ,  H01L2224/92246 ,  H01L2224/92247 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/05432 ,  H01L2224/05139 ,  H01L2924/00015 ,  H01L2224/80 ,  H01L2224/84 ,  H01L2224/85 ,  H01L2224/08 ,  H01L2224/40 ,  H01L2224/48 ,  H01L2224/03 ,  H01L2924/207 ,  H01L2224/37099

摘要： A method of manufacturing a semiconductor die, comprising the steps of: (a) forming a plurality of separate amounts of silver nanoparticle paste on a top- side of a wafer (26) such that there is an amount of silver nanoparticle paste on a first aluminum pad (28) and such that there is no silver nanoparticle paste (29) on a second aluminum pad (27); and (b) sintering the amount of silver nanoparticle paste so that the amount of silver nanoparticle paste becomes a sintered silver structure disposed on the first aluminum pad (28) and so that the second aluminum pad (27) is not covered by any sintered silver layer.

公开(公告)号：EP2835204B1

公开(公告)日：2017-03-15

申请号：EP12868928.8

申请日：2012-04-16

申请人： Tanigurogumi Corporation

发明人： TANIGURO, Katsumori

IPC分类号： B23K1/018 ,  B23K1/18 ,  B23K1/20 ,  B23K35/26 ,  H05K3/34

CPC分类号： B23K3/0607 ,  B23K1/0016 ,  B23K1/08 ,  B23K1/20 ,  B23K1/203 ,  B23K3/0646 ,  B23K3/0669 ,  B23K3/082 ,  B23K35/262 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/741 ,  H01L24/742 ,  H01L2224/03312 ,  H01L2224/03418 ,  H01L2224/036 ,  H01L2224/0381 ,  H01L2224/03821 ,  H01L2224/0401 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05111 ,  H01L2224/05147 ,  H01L2224/05582 ,  H01L2224/05611 ,  H01L2224/05647 ,  H01L2224/0569 ,  H01L2224/11312 ,  H01L2224/116 ,  H01L2224/11821 ,  H01L2224/13111 ,  H01L2224/1369 ,  H01L2224/741 ,  H01L2924/381 ,  H05K3/0085 ,  H05K3/282 ,  H05K3/3468 ,  H05K2203/081 ,  H05K2203/122 ,  H05K2203/1366 ,  H05K2203/1518 ,  Y10T428/31678 ,  H01L2224/1141 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01028 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01083 ,  H01L2924/0103 ,  H01L2924/01051 ,  H01L2224/03

公开(公告)号：EP2835204A1

公开(公告)日：2015-02-11

申请号：EP12868928.8

申请日：2012-04-16

申请人： Tanigurogumi Corporation

发明人： TANIGURO, Katsumori

IPC分类号： B23K1/018 ,  B23K1/18 ,  B23K1/20 ,  B23K35/26 ,  H05K3/34

CPC分类号： B23K3/0607 ,  B23K1/0016 ,  B23K1/08 ,  B23K1/20 ,  B23K1/203 ,  B23K3/0646 ,  B23K3/0669 ,  B23K3/082 ,  B23K35/262 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/741 ,  H01L24/742 ,  H01L2224/03312 ,  H01L2224/03418 ,  H01L2224/036 ,  H01L2224/0381 ,  H01L2224/03821 ,  H01L2224/0401 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05111 ,  H01L2224/05147 ,  H01L2224/05582 ,  H01L2224/05611 ,  H01L2224/05647 ,  H01L2224/0569 ,  H01L2224/11312 ,  H01L2224/116 ,  H01L2224/11821 ,  H01L2224/13111 ,  H01L2224/1369 ,  H01L2224/741 ,  H01L2924/381 ,  H05K3/0085 ,  H05K3/282 ,  H05K3/3468 ,  H05K2203/081 ,  H05K2203/122 ,  H05K2203/1366 ,  H05K2203/1518 ,  Y10T428/31678 ,  H01L2224/1141 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01028 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01083 ,  H01L2924/0103 ,  H01L2924/01051 ,  H01L2224/03

摘要： Provided are a soldering device and method which allow for oldering at low cost with high yield and high reliability. To solve the above problems, the soldering device has: a first processing section that immerses workpiece member 10 having copper electrode 2 in organic fatty acid-containing solution, and horizontally move immersed workpiece member 10 in organic fatty acid-containing solution 31; a second processing section having ejection unit 33 to spray a jet stream of molten solder 5a to workpiece member 10 while pulling out workpiece member 10 processed in the first processing section to space section 24 that has a pressurized steam atmosphere and is provided above organic fatty acid-containing solution 31; a third processing section having ejection unit 34 to spray organic fatty acid-containing solution 31 to excess molten solder 5a on workpiece member 10 for removal while pulling down workpiece member 10 processed in the second processing section after horizontally moving in space section 24; and a fourth processing section that picks up workpiece member 10 processed in the third processing section by pulling out from organic fatty acid-containing solution 31 after horizontally moving in organic fatty acid-containing solution 31.

摘要翻译： 提供了一种能够以低成本，高产率和高可靠性进行老化的焊接装置和方法。 为了解决上述问题，焊接装置具有：第一处理部，其将具有铜电极2的工件10浸渍在含有有机脂肪酸的溶液中，并将浸没的工件10浸入含有机脂肪酸的溶液31中; 第二处理部分具有喷射单元33，用于将熔融焊料5a的喷射流喷射到工件10上，同时将在第一处理部分中处理的工件10拉出到具有加压蒸汽气氛的空间部分24，并且设置在有机脂肪酸 含有溶液31; 具有喷射单元34的喷射单元34，用于在空间部24中水平移动之后，将在第二处理部中处理的工件10拉下的同时，将含有机脂肪酸的溶液31喷射到工件10上的多余的熔融焊料5a以进行除去; 以及第四处理部，其通过在含有机脂肪酸的溶液31中水平移动之后从含有机脂肪酸的溶液31中拉出而从第三加工部中提取加工的工件10。

公开(公告)号：EP3363048A1

公开(公告)日：2018-08-22

申请号：EP16785621.0

申请日：2016-10-06

申请人： Xilinx, Inc.

发明人： CHAWARE, Raghunandan ,  MAJUMDAR, Amitava ,  O'ROURKE, Glenn ,  SINGH, Inderjit

IPC分类号： H01L25/065 ,  H01L23/48 ,  H01L21/768 ,  H01L23/00

CPC分类号： H01L23/5385 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L22/14 ,  H01L23/3114 ,  H01L23/538 ,  H01L23/5381 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L24/92 ,  H01L24/94 ,  H01L24/96 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/18 ,  H01L2221/68327 ,  H01L2221/68331 ,  H01L2221/68372 ,  H01L2224/03312 ,  H01L2224/0332 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/17051 ,  H01L2224/17181 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/92 ,  H01L2224/94 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1461 ,  H01L2924/1515 ,  H01L2924/152 ,  H01L2924/153 ,  H01L2924/15311 ,  H01L2224/03 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L21/78 ,  H01L2221/68304 ,  H01L2224/81 ,  H01L21/56 ,  H01L21/304 ,  H01L2224/11 ,  H01L2221/68381 ,  H01L22/00 ,  H01L2224/1181

摘要： Techniques for providing a semiconductor assembly having an interconnect die for die-to-die interconnection, an IC package, a method for manufacturing, and a method for routing signals in an IC package are described. In one implementation, a semiconductor assembly is provided that includes a first interconnect die coupled to a first integrated circuit (IC) die and a second IC die by inter-die connections. The first interconnect die includes solid state circuitry that provides a signal transmission path between the IC dice.

公开(公告)号：EP3059759A1

公开(公告)日：2016-08-24

申请号：EP16154991.0

申请日：2016-02-10

申请人： Altera Corporation

发明人： LEE, Myung June

IPC分类号： H01L23/31 ,  H01L25/065 ,  H01L25/10 ,  H01L21/60 ,  H01L21/98 ,  H01L25/03

CPC分类号： H01L23/481 ,  H01L21/563 ,  H01L21/768 ,  H01L23/3114 ,  H01L24/03 ,  H01L24/05 ,  H01L24/14 ,  H01L24/16 ,  H01L24/19 ,  H01L24/92 ,  H01L25/03 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/02379 ,  H01L2224/03312 ,  H01L2224/0332 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73209 ,  H01L2224/73253 ,  H01L2224/9202 ,  H01L2224/92125 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06568 ,  H01L2225/06589 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/16235 ,  H01L2924/16251 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2924/00014

摘要： An integrated circuit package may include a first integrated circuit die (101) attached to a front surface of a second integrated circuit die (102). An intermediate layer made of a molding compound (120) is formed to surround the second integrated circuit die in a "fan-out" arrangement while leaving a surface of the second integrated circuit die exposed. Accordingly, a group of via holes (210) is then formed in the intermediate layer and filled with a conductive material (106). Such a configuration forms a dual-sided stacking structure. The stacking structure may also be applicable for package-on-package packages and fan-out wafer-level chip scale packages, in which the stacking structure is formed between two heterogeneous or homogeneous integrated circuit packages.

摘要翻译： 集成电路封装可以包括附接到第二集成电路管芯（102）的前表面的第一集成电路管芯（101）。 形成由模制化合物（120）制成的中间层，以使“第二集成电路管芯”的表面露出，从而以“扇出”布置围绕第二集成电路管芯。 因此，一组通孔（210）然后在中间层中形成并填充有导电材料（106）。 这种配置形成双面堆叠结构。 堆叠结构还可以应用于封装封装封装和扇出晶片级芯片级封装，其中堆叠结构形成在两个异质或均匀的集成电路封装之间。

公开(公告)号：EP2835204A4

公开(公告)日：2016-04-20

申请号：EP12868928

申请日：2012-04-16

申请人： TANIGUROGUMI CORP

发明人： TANIGURO KATSUMORI

IPC分类号： B23K1/018 ,  B23K1/18 ,  B23K1/20 ,  B23K35/26 ,  H05K3/34

CPC分类号： B23K3/0607 ,  B23K1/0016 ,  B23K1/08 ,  B23K1/20 ,  B23K1/203 ,  B23K3/0646 ,  B23K3/0669 ,  B23K3/082 ,  B23K35/262 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/741 ,  H01L24/742 ,  H01L2224/03312 ,  H01L2224/03418 ,  H01L2224/036 ,  H01L2224/0381 ,  H01L2224/03821 ,  H01L2224/0401 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05111 ,  H01L2224/05147 ,  H01L2224/05582 ,  H01L2224/05611 ,  H01L2224/05647 ,  H01L2224/0569 ,  H01L2224/11312 ,  H01L2224/116 ,  H01L2224/11821 ,  H01L2224/13111 ,  H01L2224/1369 ,  H01L2224/741 ,  H01L2924/381 ,  H05K3/0085 ,  H05K3/282 ,  H05K3/3468 ,  H05K2203/081 ,  H05K2203/122 ,  H05K2203/1366 ,  H05K2203/1518 ,  Y10T428/31678 ,  H01L2224/1141 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01028 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01083 ,  H01L2924/0103 ,  H01L2924/01051 ,  H01L2224/03

公开(公告)号：EP2924719A1

公开(公告)日：2015-09-30

申请号：EP14161566.6

申请日：2014-03-25

申请人： ABB Technology AG

发明人： Sivasubramaniam, Venkatesh ,  Guillon, David ,  Hajas, David ,  Sueltmann, Peter

IPC分类号： H01L21/60 ,  H01L23/373 ,  H01L25/07

CPC分类号： H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L25/072 ,  H01L2224/03312 ,  H01L2224/03418 ,  H01L2224/03422 ,  H01L2224/291 ,  H01L2224/29239 ,  H01L2224/29324 ,  H01L2224/29339 ,  H01L2224/29344 ,  H01L2224/29347 ,  H01L2224/29364 ,  H01L2224/2949 ,  H01L2224/32227 ,  H01L2224/80003 ,  H01L2224/80055 ,  H01L2224/80065 ,  H01L2224/80075 ,  H01L2224/8009 ,  H01L2224/80095 ,  H01L2224/80205 ,  H01L2224/80447 ,  H01L2224/83002 ,  H01L2224/8301 ,  H01L2224/83022 ,  H01L2224/83055 ,  H01L2224/83065 ,  H01L2224/83075 ,  H01L2224/8309 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83203 ,  H01L2224/83205 ,  H01L2224/83395 ,  H01L2224/83447 ,  H01L2224/83815 ,  H01L2224/8384 ,  H01L2924/13055 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00

摘要： The present invention relates to a method for generating a power semiconductor module (14) using a heat applying joining technique for joining two joining partners (10, 16), the heat applying joining technique comprising the steps of:
a) Providing a first joining partner (16) with a joining surface;
b) Coating the joining surface of the first joining partner (16) at least partly with a protection coating (22), the protection coating (22) having a decomposition temperature t 1 at which the material of the protection coating (22) goes into the gaseous phase;
c) Optionally applying a joining material (23) to at least a part of the protection coating (22) or to a joining surface of the second joining partner (16); and
d) Joining the joining surfaces of the two joining partners (10, 16) by applying heat with a temperature t 2 , wherein t 2 ≥ t 1 and by optionally applying pressure to the joining partners (10, 16).
One of the first and second joining partners (10, 16) is a substrate (10) and the further of the first and second joining partners (10, 16) is a power semiconductor device (16), a baseplate or a terminal. The heat applying joining technique may be a sintering process, a soldering process or an ultrasonic welding process.
Such a method provides an especially gentle and cost-saving method for heat applying joining techniques, such as die-attachment.

摘要翻译： 本发明涉及一种方法，用于使用应用连接技术用于接合两个对接件（10，16），所述热施加接合技术，包括以下步骤的热的功率半导体模块（14）：a）提供第一对接件 （16）配有一个接合表面上; b）中涂覆所述第一接合部件（16）至少部分地与具有分解温度T 1在其中保护涂层的材料（22）进入一个保护涂层（22），所述保护涂层（22）的接合表面 气相; c）任选施加接合材料（23）到至少所述保护涂层（22的一部分），或到第二对接件（16）的接合表面上; 以及d）通过与温度T 2，T worin 2‰¥吨1施加热和通过可选地将压力施加到接合伙伴（10，16）接合的两个接合部（10，16）的接合表面。 之一的第一和第二接合部件（10，16）是基底（10）和所述另外的第一和第二接合部件（10，16）是一个功率半导体器件（16），基板或终端。 施加接合技术的热量可以是烧结过程中，焊接工艺或超声焊接工艺。 这样的方法提供了爱一个用于加热的连接技术，特别是颜色温柔节省成本的方法：如附着。