摘要:
The present invention relates generally to a new interconnection and a method for making the same, and more particularly, to an elongated solder interconnection and a method for making the same. On an electronic carrier, a pad is formed on which a solder mass is deposited and capped with a metal layer, thereby forming an elongated solder interconnection. A further elongated solder interconnection can now be formed by forming a second solder mass on the first solder mass that has been capped by a metal layer. Additional elongated solder interconnection can be formed by capping the preceding solder mass and/or the last solder mass with a metal capping layer. Alternatively, the encapsulating layer can be in the form of a sidewall spacer formed on the sidewalls of the solder mass.
摘要:
A method for fabricating packaged semiconductor devices in panel format. A flat panel sheet dimensioned for a set of contiguous chips includes a stiff substrate of an insulating plate, and a tape having a surface layer of a first adhesive releasable at elevated temperatures, a core base film, and a bottom layer with a second adhesive attached to the substrate. Attaching a set onto the first adhesive layer, the chip terminals having terminals with metal bumps facing away from the first adhesive layer. Laminating low CTE insulating material to fill gaps between the bumps and to form an insulating frame surrounding the set. Grinding lamination material to expose the bumps. Plasma-cleaning assembly, sputtering uniform metal layer across assembly, optionally plating metal layer, and patterning metal layer to form rerouting traces and extended contact pads.
摘要:
A method for fabricating packaged semiconductor devices in panel format. A flat panel sheet dimensioned for a set of contiguous chips includes a stiff substrate of an insulating plate, and a tape having a surface layer of a first adhesive releasable at elevated temperatures, a core base film, and a bottom layer with a second adhesive attached to the substrate. Attaching a set onto the first adhesive layer, the chip terminals having terminals with metal bumps facing away from the first adhesive layer. Laminating low CTE insulating material to fill gaps between the bumps and to form an insulating frame surrounding the set. Grinding lamination material to expose the bumps. Plasma-cleaning assembly, sputtering uniform metal layer across assembly, optionally plating metal layer, and patterning metal layer to form rerouting traces and extended contact pads.
摘要:
A semiconductor substrate includes a semiconductor substrate body (12d) in which a wiring (16) is formed and a bonding electrode (12a) provided to protrude from a first surface (12c) of the semiconductor substrate body (12d). The bonding electrode (12a) comprises a composite including a first metal portion (14) which is provided to protrude from the first surface (12c) of the semiconductor substrate body (12d) and of which a base end portion in a protrusion direction is electrically connected to the wiring (16), and a second metal portion (15) which is formed of a second metal harder than first metal of which the first metal portion (14) is formed and which is provided to be bonded to the first metal portion (14) in a range equal to or less than a protrusion height of the first metal portion (14).
摘要:
A semiconductor device including a semiconductor element (121), an electrode pad (24) formed on the semiconductor element (121), and a bump electrode (10) conductively connected to the electrode pad (24) which includes a resin bump (12) formed on an active face (121a) of the semiconductor element (121) and a conductive layer (20) provided from the electrode pad (24) to the surface of the resin bump (12), the conductive layer (20) and the resin bump (12) being arranged without adhesion.
摘要:
A semiconductor device including a semiconductor element (121), an electrode pad (24) formed on the semiconductor element (121), and a bump electrode (10) conductively connected to the electrode pad (24) which includes a resin bump (12) formed on an active face (121a) of the semiconductor element (121) and a conductive layer (20) provided from the electrode pad (24) to the surface of the resin bump (12), the conductive layer (20) and the resin bump (12) being arranged without adhesion.