公开(公告)号：EP0335019B1

公开(公告)日：1993-05-26

申请号：EP88302802.9

申请日：1988-03-29

申请人： Director General, Agency of Industrial Science and Technology

发明人： Iwade, Shuhei c/o LSI Kenkyusho of

IPC分类号： H01L21/58

CPC分类号： H01L24/83 ,  H01L24/29 ,  H01L24/31 ,  H01L2224/29014 ,  H01L2224/29076 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/83194 ,  H01L2224/8385 ,  H01L2924/01033 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/00

公开(公告)号：EP2978015A1

公开(公告)日：2016-01-27

申请号：EP14768581.2

申请日：2014-03-13

申请人： G-Smatt Co., Ltd.

发明人： SHIN, Hak Ryul ,  LEE, Ho Joon

IPC分类号： H01L21/60 ,  B05C5/00 ,  H05K3/32 ,  H01L33/00

CPC分类号： H01L33/62 ,  H01L24/27 ,  H01L24/29 ,  H01L24/30 ,  H01L24/32 ,  H01L24/33 ,  H01L24/743 ,  H01L24/83 ,  H01L2224/27312 ,  H01L2224/29006 ,  H01L2224/29007 ,  H01L2224/29012 ,  H01L2224/29014 ,  H01L2224/29027 ,  H01L2224/29036 ,  H01L2224/30131 ,  H01L2224/30135 ,  H01L2224/30136 ,  H01L2224/30151 ,  H01L2224/30155 ,  H01L2224/30179 ,  H01L2224/30505 ,  H01L2224/32225 ,  H01L2224/33135 ,  H01L2224/33179 ,  H01L2224/33505 ,  H01L2224/743 ,  H01L2224/83192 ,  H01L2224/83194 ,  H01L2224/8385 ,  H01L2224/83851 ,  H01L2224/83874 ,  H01L2924/12041 ,  H01L2933/0066 ,  H05K3/305 ,  H05K3/321 ,  H05K2201/0108 ,  H05K2201/10106 ,  H05K2203/0126 ,  H05K2203/166 ,  Y02P70/613 ,  H01L2924/00014 ,  H01L2924/00012

摘要： Disclosed is a method of coating a conductive substrate with an adhesive, wherein the amounts and positions of conductive and non-conductive adhesives for bonding a plurality of circuit elements to the conductive substrate are set, thus preventing the spread of the adhesive from causing defects, including a poor aesthetic appearance, low electrical conductivity, and short circuits.

摘要翻译： 公开了一种用粘合剂涂覆导电衬底的方法，其中设置用于将多个电路元件接合到导电衬底的导电和非导电粘合剂的量和位置，从而防止粘合剂扩散导致缺陷， 包括美观性差，导电性低和短路。

公开(公告)号：EP2357666A3

公开(公告)日：2013-10-30

申请号：EP11000918.0

申请日：2011-02-04

申请人： International Rectifier Corporation

发明人： Cheah, Chuan ,  Briere, Michael, A.

IPC分类号： H01L23/482

CPC分类号： H01L29/41758 ,  H01L23/293 ,  H01L23/4824 ,  H01L24/05 ,  H01L24/06 ,  H01L24/29 ,  H01L24/30 ,  H01L24/32 ,  H01L24/33 ,  H01L27/088 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/4175 ,  H01L29/452 ,  H01L29/7787 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05022 ,  H01L2224/05082 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05555 ,  H01L2224/05556 ,  H01L2224/05563 ,  H01L2224/05567 ,  H01L2224/056 ,  H01L2224/05639 ,  H01L2224/0603 ,  H01L2224/0615 ,  H01L2224/0616 ,  H01L2224/06177 ,  H01L2224/131 ,  H01L2224/29005 ,  H01L2224/29014 ,  H01L2224/29023 ,  H01L2224/291 ,  H01L2224/29101 ,  H01L2224/2919 ,  H01L2224/3003 ,  H01L2224/3015 ,  H01L2224/30177 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/0665 ,  H01L2924/10253 ,  H01L2924/1306 ,  H01L2924/13064 ,  H01L2924/14 ,  H01L2924/19041 ,  H02M3/158 ,  H01L2924/01028 ,  H01L2924/00

摘要： Some exemplary embodiments of a III-nitride power device including a HEMT with multiple interconnect metal layers (130) and a solderable front metal structure (140a,140b) using solder bars for external circuit connections have been disclosed. The solderable front metal structure may comprise a tri-metal such as TiNiAg, and may be configured to expose source and drain contacts of the HEMT as alternating elongated digits or bars. Additionally, a single package may integrate multiple such HEMTs wherein the front metal structures expose alternating interdigitated source and drain contacts, which may be advantageous for DC-DC power conversion circuit designs using III-nitride devices. By using solder bars for external circuit connections, lateral conduction is enabled, thereby advantageously reducing device Rdson.

公开(公告)号：EP2677538A4

公开(公告)日：2016-02-17

申请号：EP11858569

申请日：2011-03-16

申请人： OMRON TATEISI ELECTRONICS CO

发明人： OKUNO TOSHIAKI ,  INOUE KATSUYUKI ,  FUJIWARA TAKESHI ,  SEKI TOMONORI

IPC分类号： H01L23/02

CPC分类号： H01L21/78 ,  B81C1/00269 ,  B81C1/00873 ,  B81C2203/019 ,  H01L21/50 ,  H01L23/10 ,  H01L24/03 ,  H01L24/05 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L24/94 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/04026 ,  H01L2224/05551 ,  H01L2224/05552 ,  H01L2224/05554 ,  H01L2224/05555 ,  H01L2224/05557 ,  H01L2224/2745 ,  H01L2224/27462 ,  H01L2224/29005 ,  H01L2224/29007 ,  H01L2224/29011 ,  H01L2224/29012 ,  H01L2224/29013 ,  H01L2224/29014 ,  H01L2224/29082 ,  H01L2224/29083 ,  H01L2224/29099 ,  H01L2224/2919 ,  H01L2224/3201 ,  H01L2224/32225 ,  H01L2224/83101 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/94 ,  H01L2924/0002 ,  H01L2924/1461 ,  H01L2924/163 ,  H01L2924/351 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/83 ,  H01L2224/27 ,  H01L2224/03 ,  H01L2924/00014

摘要： A wafer level package (20A) according to the present invention is provided with a base wafer (22) having a plurality of semiconductor chips (1) mounted or formed on its surface and a cover wafer (23) opposite the base wafer (22). The base wafer (22) and the cover wafer (23) are joined so as to sandwich therebetween a frame-shaped seal frame (4) which seals the periphery of each semiconductor chip. A gap (24) is formed between respective seal frames (4) of mutually adjoining semiconductor chips (1). In the gap (24) between the respective seal frames (4) of the mutually adjoining semiconductor chips (1), a partial connect part (26) is provided, which mutually and partially connects both seal frames (4). Hereby, the occurrence of a crack in a seal frame can be avoided when dicing, while providing a wafer level package, a chip size package device and a method of manufacturing a wafer level package, which can suppress the occurrence of peel-off from a wafer even when a high-temperature process is applied after a wet process or after liquid cleaning.

摘要翻译： 一种晶片级封装（20A）雅丁到，本发明是设置有具有半导体芯片有多个（1）安装或形成在其表面与基底晶片相对的晶片盖（23）上的基体晶片（22）（22） ， 基底晶片（22）和所述盖晶片（23）以夹着框状密封框架（4），其密封每个半导体芯片的周边之间接合，从而在那里。 的间隙（24）是相互邻接的半导体芯片（1）所形成respectivement密封帧（4）之间。 在相互邻接的半导体芯片（1）的密封respectivement帧（4）之间的间隙（24），部分连接部分（26）被提供，其相互并部分地连接两个密封帧（4）。 由此，在密封框架的裂纹的发生，可避免当切割，同时提供了晶片级封装，芯片尺寸封装器件及其制造晶片级封装，其可以从一个抑制剥离的发生的方法 晶片甚至当高温工艺的湿式处理之后或清洗液体之后施用。

公开(公告)号：EP1547162B1

公开(公告)日：2015-03-04

申请号：EP03750322.4

申请日：2003-09-05

申请人： OSRAM Opto Semiconductors GmbH

发明人： EISERT, Dominik ,  ILLEK, Stefan ,  SCHMID, Wolfgang

IPC分类号： H01L33/00

CPC分类号： H01L33/20 ,  H01L23/3677 ,  H01L24/29 ,  H01L24/83 ,  H01L24/95 ,  H01L2224/29014 ,  H01L2224/29124 ,  H01L2224/29164 ,  H01L2224/29169 ,  H01L2224/83203 ,  H01L2924/12042 ,  H01L2924/351 ,  H01L2924/3512 ,  H01L2924/00

公开(公告)号：EP2357666A2

公开(公告)日：2011-08-17

申请号：EP11000918.0

申请日：2011-02-04

申请人： International Rectifier Corporation

发明人： Cheah, Chuan ,  Briere, Michael, A.

IPC分类号： H01L23/482

CPC分类号： H01L29/41758 ,  H01L23/293 ,  H01L23/4824 ,  H01L24/05 ,  H01L24/06 ,  H01L24/29 ,  H01L24/30 ,  H01L24/32 ,  H01L24/33 ,  H01L27/088 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/4175 ,  H01L29/452 ,  H01L29/7787 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05022 ,  H01L2224/05082 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05555 ,  H01L2224/05556 ,  H01L2224/05563 ,  H01L2224/05567 ,  H01L2224/056 ,  H01L2224/05639 ,  H01L2224/0603 ,  H01L2224/0615 ,  H01L2224/0616 ,  H01L2224/06177 ,  H01L2224/131 ,  H01L2224/29005 ,  H01L2224/29014 ,  H01L2224/29023 ,  H01L2224/291 ,  H01L2224/29101 ,  H01L2224/2919 ,  H01L2224/3003 ,  H01L2224/3015 ,  H01L2224/30177 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/0665 ,  H01L2924/10253 ,  H01L2924/1306 ,  H01L2924/13064 ,  H01L2924/14 ,  H01L2924/19041 ,  H02M3/158 ,  H01L2924/01028 ,  H01L2924/00

摘要： Some exemplary embodiments of a III-nitride power device including a HEMT with multiple interconnect metal layers (130) and a solderable front metal structure (140a,140b) using solder bars for external circuit connections have been disclosed. The solderable front metal structure may comprise a tri-metal such as TiNiAg, and may be configured to expose source and drain contacts of the HEMT as alternating elongated digits or bars. Additionally, a single package may integrate multiple such HEMTs wherein the front metal structures expose alternating interdigitated source and drain contacts, which may be advantageous for DC-DC power conversion circuit designs using III-nitride devices. By using solder bars for external circuit connections, lateral conduction is enabled, thereby advantageously reducing device Rdson.

摘要翻译： 已经公开了使用用于外部电路连接的焊料条的包括具有多个互连金属层（130）和可焊接前金属结构（140a，140b）的HEMT的III族氮化物功率器件的一些示例性实施例。 可焊接的前金属结构可以包括诸如TiNiAg的三金属，并且可以被配置为暴露HEMT的源极和漏极接触作为交替的细长数字或条。 另外，单个封装可以集成多个这样的HEMT，其中前金属结构暴露出交替的指示的源极和漏极触点，这对于使用III族氮化物器件的DC-DC功率转换电路设计是有利的。 通过使用焊条进行外部电路连接，可以进行横向导通，从而有利于减少器件Rdson。

公开(公告)号：EP2978015A4

公开(公告)日：2016-12-07

申请号：EP14768581

申请日：2014-03-13

申请人： G-SMATT CO LTD

发明人： SHIN HAK RYUL ,  LEE HO JOON

IPC分类号： H05K3/32 ,  H01L23/00 ,  H05K3/30

CPC分类号： H01L33/62 ,  H01L24/27 ,  H01L24/29 ,  H01L24/30 ,  H01L24/32 ,  H01L24/33 ,  H01L24/743 ,  H01L24/83 ,  H01L2224/27312 ,  H01L2224/29006 ,  H01L2224/29007 ,  H01L2224/29012 ,  H01L2224/29014 ,  H01L2224/29027 ,  H01L2224/29036 ,  H01L2224/30131 ,  H01L2224/30135 ,  H01L2224/30136 ,  H01L2224/30151 ,  H01L2224/30155 ,  H01L2224/30179 ,  H01L2224/30505 ,  H01L2224/32225 ,  H01L2224/33135 ,  H01L2224/33179 ,  H01L2224/33505 ,  H01L2224/743 ,  H01L2224/83192 ,  H01L2224/83194 ,  H01L2224/8385 ,  H01L2224/83851 ,  H01L2224/83874 ,  H01L2924/12041 ,  H01L2933/0066 ,  H05K3/305 ,  H05K3/321 ,  H05K2201/0108 ,  H05K2201/10106 ,  H05K2203/0126 ,  H05K2203/166 ,  Y02P70/613 ,  H01L2924/00014 ,  H01L2924/00012

公开(公告)号：EP2677538A1

公开(公告)日：2013-12-25

申请号：EP11858569.4

申请日：2011-03-16

申请人： Omron Corporation

发明人： OKUNO, Toshiaki ,  INOUE, Katsuyuki ,  FUJIWARA, Takeshi ,  SEKI, Tomonori

IPC分类号： H01L23/02

CPC分类号： H01L21/78 ,  B81C1/00269 ,  B81C1/00873 ,  B81C2203/019 ,  H01L21/50 ,  H01L23/10 ,  H01L24/03 ,  H01L24/05 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L24/94 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/04026 ,  H01L2224/05551 ,  H01L2224/05552 ,  H01L2224/05554 ,  H01L2224/05555 ,  H01L2224/05557 ,  H01L2224/2745 ,  H01L2224/27462 ,  H01L2224/29005 ,  H01L2224/29007 ,  H01L2224/29011 ,  H01L2224/29012 ,  H01L2224/29013 ,  H01L2224/29014 ,  H01L2224/29082 ,  H01L2224/29083 ,  H01L2224/29099 ,  H01L2224/2919 ,  H01L2224/3201 ,  H01L2224/32225 ,  H01L2224/83101 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/94 ,  H01L2924/0002 ,  H01L2924/1461 ,  H01L2924/163 ,  H01L2924/351 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/83 ,  H01L2224/27 ,  H01L2224/03 ,  H01L2924/00014

摘要： A wafer level package (20A) according to the present invention is provided with a base wafer (22) having a plurality of semiconductor chips (1) mounted or formed on its surface and a cover wafer (23) opposite the base wafer (22). The base wafer (22) and the cover wafer (23) are joined so as to sandwich therebetween a frame-shaped seal frame (4) which seals the periphery of each semiconductor chip. A gap (24) is formed between respective seal frames (4) of mutually adjoining semiconductor chips (1). In the gap (24) between the respective seal frames (4) of the mutually adjoining semiconductor chips (1), a partial connect part (26) is provided, which mutually and partially connects both seal frames (4). Hereby, the occurrence of a crack in a seal frame can be avoided when dicing, while providing a wafer level package, a chip size package device and a method of manufacturing a wafer level package, which can suppress the occurrence of peel-off from a wafer even when a high-temperature process is applied after a wet process or after liquid cleaning.

公开(公告)号：EP1547162A2

公开(公告)日：2005-06-29

申请号：EP03750322.4

申请日：2003-09-05

申请人： Osram Opto Semiconductors GmbH

发明人： EISERT, Dominik ,  ILLEK, Stefan ,  SCHMID, Wolfgang

IPC分类号： H01L33/00

CPC分类号： H01L33/20 ,  H01L23/3677 ,  H01L24/29 ,  H01L24/83 ,  H01L24/95 ,  H01L2224/29014 ,  H01L2224/29124 ,  H01L2224/29164 ,  H01L2224/29169 ,  H01L2224/83203 ,  H01L2924/12042 ,  H01L2924/351 ,  H01L2924/3512 ,  H01L2924/00

摘要： The aim of the invention is to reduce or compensate thermal stress created within a semiconductor component. Said aim is achieved by a semiconductor component comprising a light-emitting semiconductor layer or a light-emitting semiconductor element, two contact points, and a vertically or horizontally structured carrier substrate, and a method for producing a semiconductor component. Thermal stress is created by changes in temperature during processing and operation as well as due to the different coefficients of expansion of the semiconductor and the carrier substrate. The inventive carrier substrate is structured in such a way that thermal stress is reduced or compensated to a degree that is sufficient for the component not to break down.

公开(公告)号：EP0335019A1

公开(公告)日：1989-10-04

申请号：EP88302802.9

申请日：1988-03-29

申请人： Director General, Agency of Industrial Science and Technology

发明人： Iwade, Shuhei c/o LSI Kenkyusho of

IPC分类号： H01L21/58

CPC分类号： H01L24/83 ,  H01L24/29 ,  H01L24/31 ,  H01L2224/29014 ,  H01L2224/29076 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/83194 ,  H01L2224/8385 ,  H01L2924/01033 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/00

摘要： A semiconductor device comprising a semiconductor chip (2) attached to a substrate (3) by two kinds of bonding agents (17,18), one (17) of which the rigid and disposed at the central region of the semiconductor chip (2), the other (18) of which is disposed around the rigid bonding agent and which is sufficiently resilient to accommodate thermal expansion differences between the semiconductor chip (2) and the substrate (3).

摘要翻译： 一种半导体器件，包括通过两种粘合剂（17,18）附接到基板（3）的半导体芯片（2），其中刚性并且设置在半导体芯片（2）的中心区域的一个（17） ，另一个（18）设置在刚性粘合剂的周围，并且其具有足够的弹性以适应半导体芯片（2）和基板（3）之间的热膨胀差异。