公开(公告)号：EP3300464A1

公开(公告)日：2018-03-28

申请号：EP17197530.3

申请日：2009-11-09

Applicant: Nitto Denko Corporation

Inventor： ISHII, Jun ,  NAITOU, Toshiki ,  HONJO, Mitsuru

IPC: H05K1/02 ,  H05K3/46 ,  G11B5/48

CPC classification number: H05K3/4685 ,  G11B5/484 ,  G11B5/486 ,  H05K1/0228 ,  H05K1/0245 ,  H05K1/025 ,  H05K1/0265 ,  H05K1/056 ,  H05K3/06 ,  H05K2201/09236 ,  H05K2201/09254 ,  H05K2201/09509 ,  H05K2201/09554 ,  H05K2201/09627 ,  H05K2201/0979 ,  H05K2203/0323 ,  Y10T29/49155

Abstract: An end of a first line and an end of a second line of a first write wiring pattern are arranged on both sides of a third line of a second write wiring pattern. Circular connection portions are provided at the ends of the first line and the second line. In addition, through holes are formed in respective portions of a base insulating layer below the connection portions. Each connection portion comes in contact with a connecting region of a suspension body within the through hole.

Abstract translation: 第一写入布线图案的第一行的末端和第二行的末端布置在第二写入布线图案的第三行的两侧。 在第一行和第二行的末端提供圆形连接部分。 另外，在连接部分下方的基底绝缘层的各个部分中形成通孔。 每个连接部分与通孔内的悬挂体的连接区域接触。

公开(公告)号：EP3013127A1

公开(公告)日：2016-04-27

申请号：EP15191149.2

申请日：2008-03-25

Applicant: Huawei Technologies Co., Ltd.

Inventor： Shen, Xiaolan ,  Ye, Qingsong ,  Wei, Konggang

IPC: H05K1/02 ,  H05K3/42 ,  H05K3/46

CPC classification number: H05K1/0218 ,  H05K1/0237 ,  H05K1/025 ,  H05K1/0298 ,  H05K3/429 ,  H05K3/4602 ,  H05K2201/0191 ,  H05K2201/0715 ,  H05K2201/09536 ,  H05K2201/09627

Abstract: A printed circuit board and a design method thereof are disclosed. The design method includes: wiring signal lines on an area basis at inner layers adjacent to outer surface layers; arranging the outer surface layers with no wiring or few wirings and interconnecting the outer surface layers through through vias, so that the outer surface layers function as a primary ground; and setting parameters of a line width and a layer height to control a target impedance value. The printed circuit board includes outer surface layers and two inner layers therebetween. The inner layers adjacent to the outer surface layers are used for arranging signal lines on an area basis; and the outer surface layers are arranged with no wiring or few wirings and are interconnected as a primary ground through through vias. The invention also discloses a mainboard of a terminal product using the printed circuit board.

Abstract translation: 公开了印刷电路板及其设计方法。 该设计方法包括：在与外表面层相邻的内层处基于区域布线信号线; 将外表面层布置成没有布线或几条布线，并且通过通孔将外表面层互连，使得外表面层用作主地面; 并设置线宽和层高的参数以控制目标阻抗值。 印刷电路板包括外表面层和它们之间的两个内层。 与外表面层相邻的内层用于在区域的基础上布置信号线; 并且外表面层布置成没有布线或几个布线，并且通过通孔作为主地相互连接。 本发明还公开了使用印刷电路板的终端产品的主板。

公开(公告)号：EP2147464B1

公开(公告)日：2015-10-21

申请号：EP08736587.0

申请日：2008-04-25

Applicant: International Business Machines Corporation

Inventor： WEEKLY, Roger, Donell ,  HARIDASS, Anand ,  CHUN, Sungjun

IPC: H05K1/02 ,  H01L23/66 ,  H01L23/498 ,  H05K3/46 ,  H05K1/11

CPC classification number: H01L21/76879 ,  H01L23/66 ,  H01L2224/16225 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/3011 ,  H05K1/0253 ,  H05K1/112 ,  H05K3/4602 ,  H05K2201/09536 ,  H05K2201/09627 ,  H05K2201/0969 ,  H01L2224/0401

Abstract: An integrated circuit substrate is designed and fabricated with a selectively applied transmission line reference plane metal layer to achieve signal path shielding and isolation, while avoiding drops in impedance due to capacitance between large diameter vias and the transmission line reference plane metal layer. The transmission line reference plane defines voids above (or below) the signal-bearing plated-through holes (PTHs) that pass through a rigid substrate core, so that the signals are not degraded by an impedance mismatch that would otherwise be caused by shunt capacitance from the top (or bottom) of the signal-bearing PTHs to the transmission line reference plane. For voltage-plane bearing PTHs, no voids are introduced, so that signal path conductors can be routed above or adjacent to the voltage-plane bearing PTHs, with the transmission line reference plane preventing shunt capacitance between the signal path conductors and the PTHs.

公开(公告)号：EP1455557B1

公开(公告)日：2013-02-27

申请号：EP03023937.0

申请日：2003-10-22

Applicant: ROBERT BOSCH GMBH

Inventor： Roozenbeck, Herman ,  Bayer, Uwe

IPC: H05K1/02 ,  H05K1/11

CPC classification number: H05K1/0216 ,  H05K1/0231 ,  H05K1/115 ,  H05K1/117 ,  H05K1/18 ,  H05K2201/0715 ,  H05K2201/09254 ,  H05K2201/09318 ,  H05K2201/09345 ,  H05K2201/09627 ,  H05K2201/10689

公开(公告)号：EP1845762B1

公开(公告)日：2011-05-25

申请号：EP06712598.9

申请日：2006-01-30

Applicant: IBIDEN CO., LTD.

Inventor： WU, Youhong

IPC: H05K3/46 ,  H05K3/18

CPC classification number: H05K1/115 ,  H05K3/4602 ,  H05K2201/0347 ,  H05K2201/0352 ,  H05K2201/09454 ,  H05K2201/09563 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/09627 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: [PROBLEMS] To provide a multilayer printed wiring board which does not deteriorate connection reliability by forming a filled via directly above a small-diameter filled via. [MEANS FOR SOLVING PROBLEMS] A stress applied on the filled via (60) formed on covering plating layers (36a, 36d) is larger than that applied on a filled via (160) formed on a second interlayer resin insulating layer (150) during a heat cycle. Thus, a bottom diameter (d1) of the filled via (60) is made larger than a bottom diameter (d2) of the filled via (160) formed directly above.

Abstract translation: 本发明提供一种多层印刷线路板，其通过在小直径填充通路正上方形成填充通路而不会使连接可靠性降低。 [解决问题的方法]施加在形成在覆盖镀层（36a，36d）上的填充通孔（60）上的应力大于施加在形成在第二层间树脂绝缘层（150）上的填充通孔（160） 一个热循环。 因此，填充通孔（60）的底部直径（d1）大于直接形成在上方的填充通孔（160）的底部直径（d2）。

公开(公告)号：EP2163144A1

公开(公告)日：2010-03-17

申请号：EP07846765.1

申请日：2007-11-23

Applicant: Sony Ericsson Mobile Communications AB

Inventor： LUNDELL, Patrik ,  ESKILSSON, Stefan ,  AHLBERG,Thomas

IPC: H05K1/00 ,  H05K1/02 ,  H01P3/08

CPC classification number: H05K1/0253 ,  H05K1/0298 ,  H05K2201/0191 ,  H05K2201/09327 ,  H05K2201/09336 ,  H05K2201/09627 ,  Y10T29/49155

Abstract: A multilayered printed wiring board, a multilayer PWB, and a method for manufacturing the same. The multilayer PWB comprises a first main surface (201) and an opposing second main surface (202), where the multilayer PWB has a height (h) being defined, by the distance from the first main surface to the opposing second main surface. The two surfaces and the height together define the thickness of the multilayer PWB. The multilayer PWB comprises a reference ground plane, a microstrip conductor (210) separated from the reference ground plane (230') by a first dielectric layer (250) and a stripline conductor (220) connected with the microstrip conductor and being separated from the reference ground plane (230' ') by a second dielectric layer (260). The reference ground plane is formed by two or more different partial reference (230',230' ') ground planes positioned at different layers of the multilayer PWB. Furthermore, the reference ground plane is moveable from the first partial reference ground plane to the second partial reference ground plane when a signal current transits from the microstrip conductor to the stripline conductor, and vice versa.

公开(公告)号：EP2034810A1

公开(公告)日：2009-03-11

申请号：EP06822140.7

申请日：2006-10-24

Applicant: IBIDEN CO., LTD.

Inventor： TAKAHASHI, Michimasa ,  AOYAMA, Masakazu

IPC: H05K3/46

CPC classification number: H05K3/4644 ,  H05K3/0035 ,  H05K3/4602 ,  H05K3/4652 ,  H05K3/4691 ,  H05K2201/0187 ,  H05K2201/09127 ,  H05K2201/09509 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/09627

Abstract: A flexible substrate 13 having conductor patterns 132 and 133, and a non-flexible substrate 111 with rigidity are disposed adjacent to each other in the horizontal direction. The flexible substrate 13 and the non-flexible substrate 111 are covered with insulating layers 111 and 113 so that at least a portion of the flexible substrate is exposed. Vias 116 and 141 are formed in the insulating layers 111 and 116 so as to reach the conductor patterns 132 and 133 of the flexible substrate 13, and wirings 117 and 142 are formed by plating to reach the conductor patterns 132 and 133 through the vias 116 and 141. The insulating layers 114, 115, 144, and 145 are laminated on the insulating layers 111 and 113, and circuits 123 and 150 are formed for connection of wiring.

Abstract translation: 具有导体图案132和133的柔性基板13和具有刚性的非柔性基板111在水平方向上彼此相邻布置。 柔性基板13和非柔性基板111被绝缘层111和113覆盖，使得柔性基板的至少一部分露出。 通孔116和141形成在绝缘层111和116中以便到达柔性基板13的导体图案132和133，并且布线117和142通过电镀形成以通过通孔116到达导体图案132和133 绝缘层114,115,144和145层叠在绝缘层111和113上，并且形成电路123和150用于布线的连接。

公开(公告)号：EP1924321A1

公开(公告)日：2008-05-28

申请号：EP06814688.5

申请日：2006-09-15

Applicant: MEDTRONIC, INC.

Inventor： BURDON, Jeremy W. ,  YAMAMOTO, Joyce K.

IPC: A61N1/375 ,  H01L23/15 ,  H01L23/498

CPC classification number: A61N1/3754 ,  H01L23/10 ,  H01L2924/0002 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/15192 ,  H01L2924/16152 ,  H01L2924/16251 ,  H01L2924/3011 ,  H05K1/0306 ,  H05K1/115 ,  H05K3/4611 ,  H05K3/4629 ,  H05K2201/09627 ,  H05K2201/09709 ,  H01L2924/00

Abstract: The invention includes a family of miniaturized, hermetic electrical feedthrough assemblies adapted for implantation within a biological system. An electrical feedthrough assembly according to the invention can be used as a component of an implantable medical device (IMD) such as an implantable pulse generator, cardioverter-defibrillator, physiologic sensor, drug-delivery system and the like. Such assemblies require biocompatibility and resistance to degradation under applied bias current or voltage. Such an assembly is fabricated by interconnected electrical pathways, or vias, of a conductive metallic paste disposed between ceramic green-state material. The layers are stacked together and sintered to form a substantially monolithic dielectric structure with at least one embedded metallization pathway extending through the structure. The metallization pathway reliably conducts electrical signals even when exposed to body fluids and tissue and providing electrical communication between internal IMD circuitry and active electrical components and/or circuitry coupled to the exterior of an IMD.

公开(公告)号：EP1568099B1

公开(公告)日：2008-04-16

申请号：EP03781616.2

申请日：2003-10-31

Applicant: Intel Corporation

Inventor： TRIPATHI, Alok ,  MILLER, Dennis

IPC: H01P5/02 ,  H01P5/18

CPC classification number: H05K1/0245 ,  H05K1/023 ,  H05K1/0239 ,  H05K2201/09236 ,  H05K2201/09627 ,  H05K2201/09727 ,  H05K2201/10022

Abstract: An apparatus that includes a first conducting strip having a narrowed width where the first conducting strip also acts as a first electrode for a first tapping capacitance. The first tapping capacitance has a second electrode that is: 1) parallel to the first conducting strip; and 2) closer to the first conducting strip than a second conducting strip. The second conducting strip is parallel to the first conducting strip and has a narrowed width where the second conducting strip also acts as a first electrode for a second tapping capacitance. The second tapping capacitance has a second electrode that is: 1) parallel to the second conducting strip; and 2) closer to the second conducting strip than the first conducting strip.

公开(公告)号：EP1895589A2

公开(公告)日：2008-03-05

申请号：EP07122506.4

申请日：1998-09-28

Applicant: IBIDEN CO., LTD.

Inventor： The designation of the inventor has not yet been filed

IPC: H01L23/50 ,  H01L23/498 ,  H05K1/02 ,  H05K1/11 ,  H05K3/34 ,  H05K3/46

CPC classification number: H01L23/50 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15173 ,  H01L2924/15311 ,  H05K1/0271 ,  H05K1/114 ,  H05K1/116 ,  H05K3/3457 ,  H05K3/4602 ,  H05K3/4644 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/09627 ,  H05K2201/09781 ,  H05K2201/10734 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05599

Abstract: The invention relates to a package board composed as a multi-layer wiring board, comprising a plurality of conductor circuits (158U,158D) formed in an outermost layer, an insulating layer (150) for supporting a plurality of said conductor circuits formed in said outermost layer and a plurality of inner layer conductor circuits formed under said insulating layer, wherein a plurality of said inner layer conductor circuits are a power supply layer (58U) and/or a ground layer (58D), a soldering bump (76U,76D) is formed, through said insulting layer, on each via-hole (160U,160D) connected to an inner layer conductor circuit.

Abstract translation: 本发明涉及一种作为多层布线板构成的封装板，包括形成在最外层的多个导体电路（158U，158D），用于支撑形成在所述第一层中的多个所述导体电路的绝缘层（150） 最外层和形成在所述绝缘层下面的多个内层导体电路，其中多个所述内层导体电路是电源层（58U）和/或接地层（58D），焊接凸块（76U，76D ）通过所述绝缘层形成在连接到内层导体电路的每个通孔（160U，160D）上。