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    SEMICONDUCTOR DEVICE
    1.
    发明专利
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：JP2006186304A

    公开(公告)日：2006-07-13

    申请号：JP2005193748

    申请日：2005-07-01

    Applicant: DENSO CORP

    Inventor： KONDO ICHIJI ,  MIZUNO YOSHIAKI ,  MIURA SHOJI ,  FUKAYA AKINARI ,  TOMISAKA MANABU

    IPC: H01L21/60

    Abstract: PROBLEM TO BE SOLVED: To allow a metal electrode to be patterned more easily and reliably at lower costs when compared to conventional methods, in a semiconductor device in which a metal electrode for connection is formed on an aluminum electrode formed on one surface of a semiconductor substrate. SOLUTION: An aluminum electrode 11 and a protection film 12 are sequentially formed on the surface 1a of a semiconductor substrate 1, and then an opening 12a is formed in the protection film 12, and subsequently a metal electrode 13 is formed on the surface 11a of the aluminum electrode 11 exposed through the opening 12a, thereby forming a semiconductor device. A level difference is formed so that the surface 11a of the aluminum electrode 11 exposed through the opening 12a is recessed relative to the top surface of the protection film 12. The metal electrode 13 is formed only on the surface 11a of the aluminum electrode 11, which is exposed through the opening 12a, and the side surface 12b of the protection film 12 by patterning the film formed on the aluminum electrode 11 and the protection film 12 by means of cutting, grinding, or polishing. COPYRIGHT: (C)2006,JPO&NCIPI

    Process for producing semiconductor chip
    2.
    发明专利
    Process for producing semiconductor chip 有权
    生产半导体芯片的工艺

    公开(公告)号：JP2005244165A

    公开(公告)日：2005-09-08

    申请号：JP2004291396

    申请日：2004-10-04

    Applicant: Denso Corp ,  株式会社デンソー

    Inventor： HIRANO NAOHIKO ,  MIURA SHOJI ,  NIIMI AKIHIRO

    IPC: H01L21/28 ,  H01L21/44 ,  H01L21/4763 ,  H01L21/50 ,  H01L21/56 ,  H01L21/60 ,  H01L21/768 ,  H01L21/78 ,  H01L23/12 ,  H01L23/29 ,  H01L29/739

    CPC classification number: H01L21/76838 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/00014 ,  H01L2924/00

    Abstract: PROBLEM TO BE SOLVED: To suppress warp of a semiconductor wafer becoming a semiconductor chip as much as possible at the time of producing the semiconductor chip in a semiconductor device being produced by arranging heat sinks on the opposite major surface sides of the semiconductor chip having electrodes on the major surface and the major rear surface and then resin molding the device substantially entirely. SOLUTION: A semiconductor wafer 100 becoming a semiconductor chip 10 having a major surface and a major rear surface matching those of the semiconductor chip 10 is prepared, a rear surface electrode 13 is formed on the major rear surface of the semiconductor wafer 100, and under a state where the major rear surface of the semiconductor wafer 100 is secured to a substrate 200 for supporting the semiconductor wafer 100, a surface electrode 12 is formed on the major surface of the semiconductor wafer 100, the supporting substrate 200 is removed and the semiconductor wafer 100 is cut thus forming the semiconductor chip 10. COPYRIGHT: (C)2005,JPO&NCIPI

    Abstract translation: 要解决的问题：为了在半导体器件中制造半导体芯片时尽可能多地抑制半导体晶片变为半导体芯片的翘曲，该半导体器件是通过将散热器布置在半导体的相对主表面侧上而制造的 芯片在主表面和主后表面上具有电极，然后基本上完全树脂成型该器件。 解决方案：制备半导体晶片100，其具有与半导体芯片10的主表面和主后表面匹配的主表面和主后表面的半导体芯片10，后表面电极13形成在半导体晶片100的主后表面上 并且在将半导体晶片100的主后表面固定到用于支撑半导体晶片100的基板200的状态下，在半导体晶片100的主表面上形成表面电极12，去除支撑基板200 并切割半导体晶片100，从而形成半导体芯片10.版权所有（C）2005，JPO＆NCIPI

    SEMICONDUCTOR DEVICE
    3.
    发明专利
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：JP2003258166A

    公开(公告)日：2003-09-12

    申请号：JP2002312615

    申请日：2002-10-28

    Applicant: DENSO CORP

    Inventor： HIRANO NAOHIKO ,  TEJIMA TAKANORI ,  NAKASE YOSHIMI ,  MIURA SHOJI

    IPC: H01L23/28 ,  H01L23/29 ,  H01L23/433 ,  H01L23/48 ,  H01L23/495 ,  H01L23/34 ,  H01L23/36 ,  H01L25/07 ,  H01L25/18

    Abstract: PROBLEM TO BE SOLVED: To reduce production cost, while enhancing heat dissipation properties by simplifying insulation arrangement or heat transfer arrangement. SOLUTION: The semiconductor device 11 comprises a first metal body 13 bonded to the back side of a semiconductor element 12 and serving as an electrode and a heat dissipation, a second metal body 14 bonded to the surface side of the semiconductor element 12 and serving as an electrode and a heat dissipation, where the entire body is molded body resin 17. The first metal body 13 and the second metal body 14 are exposed to one planar part 19 of the molding 18. According to the arrangement, insulation arrangement or heat transfer arrangement is required only for the first metal body 13 and for the second metal body 14 exposed to one planar part 19 of the molding 18. COPYRIGHT: (C)2003,JPO

    INSULATED-GATE POWER IC
    4.
    发明专利
    INSULATED-GATE POWER IC 失效

    公开(公告)号：JP2001352066A

    公开(公告)日：2001-12-21

    申请号：JP2000346542

    申请日：2000-11-14

    Applicant: DENSO CORP

    Inventor： MIURA SHOJI ,  SUZUKI MIKIMASA ,  SUZUKI FUMINARI ,  KUROYANAGI AKIRA ,  ISENO AKITOSHI ,  NAKASE YOSHIMI

    IPC: H01L29/739 ,  H01L29/78

    Abstract: PROBLEM TO BE SOLVED: To prevent decrease in the non-defective rate, simplify the processing of a lead frame, reduce the size of a package, even if the chip size is increased, and to make an IC applicable even to a device of such a structure as to be cooled from the surface of a chip. SOLUTION: This insulated-gated power IC comprises a plurality of cell blocks 12 formed on a chip 1, a plurality of independent gate electrodes formed on the cell blocks 12 respectively, a plurality of gate pads 18 connected to the gate electrodes formed on the chip 1 respectively, and a plurality of pads 19, having the emitter potential formed on the chip 1 which are formed so as to be adjacent to the gate pads 18. Due to this structure, gate pads 18 of cell blocks 12 of defective products can be wire-bonded to pads 19 having emitter potential.

    SEMICONDUCTOR DEVICE
    5.
    发明专利
    SEMICONDUCTOR DEVICE 失效

    公开(公告)号：JPH09167830A

    公开(公告)日：1997-06-24

    申请号：JP31929796

    申请日：1996-11-29

    Applicant: DENSO CORP

    Inventor： ISOBE YOSHIHIKO ,  IIDA MAKIO ,  MIURA SHOJI ,  KAJIURA KEIZO ,  SUZUKI MIKIMASA ,  SAITO MASAMI

    IPC: H01L27/04 ,  H01L21/822

    Abstract: PROBLEM TO BE SOLVED: To realize a semiconductor device equipped with resistors and capacitors suitable for integration. SOLUTION: A silicon oxide film 5 is formed on a P-type silicon substrate 1, and an N -type diffusion region 7a is formed on the surface of the P-type silicon substrate 1. The silicon oxide film 5 is partially removed, a silicon thermal oxide film 20 is formed, and a thin film resistor 9 is formed thereon. By this setup, a capacitor is formed of the thin film resistor 9 and an N -type diffusion region 7a formed on the surface of a P -type semiconductor substrate. The capacitor can be formed under a region where the thin film resistor 9 is formed and suitable for integration.

    Inverter circuit
    7.
    发明专利
    Inverter circuit 有权
    逆变器电路

    公开(公告)号：JP2005287227A

    公开(公告)日：2005-10-13

    申请号：JP2004099473

    申请日：2004-03-30

    Applicant: Denso Corp ,  株式会社デンソー

    Inventor： KATO NOBUYUKI ,  MIURA SHOJI ,  HIRANO NAOHIKO

    IPC: H02M1/00 ,  H02M7/5387

    Abstract: PROBLEM TO BE SOLVED: To make temperatures of a plurality of semiconductor elements substantially equal even if there are variations in characteristics of the plurality of the semiconductor elements connected in parallel. SOLUTION: This inverter circuit 1 is composed of a circuit constitution 7 formed by connecting the two or more semiconductor elements 6 in parallel, and characterized in that the semiconductor element 6 used for the two or more semiconductor elements 6 has a characteristic that a current value at a cross point where a normal temperature Vce-Ice characteristic and a high temperature Vce-Ice characteristic intersect with each other is smaller than a normal energization current value. COPYRIGHT: (C)2006,JPO&NCIPI

    Abstract translation: 要解决的问题：即使并联连接的多个半导体元件的特性变化，也使多个半导体元件的温度基本相等。 解决方案：该逆变器电路1由并联连接两个以上的半导体元件6而形成的电路结构7构成，其特征在于，用于两个以上的半导体元件6的半导体元件6具有如下特征： 常温Vce-Ice特性和高温Vce-Ice特性相交的交叉点处的电流值小于通常的通电电流值。 版权所有（C）2006，JPO＆NCIPI

    Semiconductor device
    8.
    发明专利
    Semiconductor device 审中-公开
    半导体器件

    公开(公告)号：JP2005268496A

    公开(公告)日：2005-09-29

    申请号：JP2004078243

    申请日：2004-03-18

    Applicant: Denso Corp ,  株式会社デンソー

    Inventor： MIURA SHOJI ,  OZEKI YOSHIHIKO ,  NAKASE YOSHIMI ,  KATO NOBUYUKI

    IPC: H01L23/40

    CPC classification number: H01L24/33 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/014 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

    Abstract: PROBLEM TO BE SOLVED: To employ a structure of radiating heat from both upper and lower faces of a semiconductor element, while obtaining a sufficient heat radiation performance. SOLUTION: A semiconductor device 11 is constituted in such a way that two heatsinks 13, 14 are solder-joined to upper and lower faces of a semiconductor element 12, by interposing a radiation block 15 having an external shape which is smaller than the semiconductor element 12, between the upper face of the semiconductor element 12 and the upper heatsink 14. A region where a channel of a main cell is formed or a region where a channel current of the main cell flows on the upper face of the semiconductor element 12 is disposed below the radiation block 15, and also this structure is not formed away from the end of the radiation block 15 by about 1.0 mm or more. With this structure, a radiation path of heat generated in the main cell is directed to a vertical direction of the element, thereby obtaining the sufficient heat radiation performance. COPYRIGHT: (C)2005,JPO&NCIPI

    Abstract translation: 要解决的问题：采用从半导体元件的上表面和下表面散热的结构，同时获得足够的散热性能。 解决方案：半导体器件11被构造成使得两个散热器13,14被焊接到半导体元件12的上表面和下表面，通过插入具有小于 半导体元件12，位于半导体元件12的上表面和上部散热器14之间。形成主单元的沟道的区域或主单元的沟道电流在半导体的上表面上流动的区域 元件12设置在辐射块15的下方，并且也不将该结构远离辐射块15的端部形成大约1.0mm或更大。 利用这种结构，在主单元中产生的热的辐射路径被引向元件的垂直方向，从而获得足够的散热性能。 版权所有（C）2005，JPO＆NCIPI

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