公开(公告)号：US08889507B2

公开(公告)日：2014-11-18

申请号：US11765971

申请日：2007-06-20

申请人： Chih-Ta Wu ,  Jason Lee ,  Chung Chien Wang ,  Hsing-Lien Lin ,  Yu-Jen Wang ,  Yeur-Luen Tu ,  Chern-Yow Hsu ,  Yuan-Hung Liu ,  Chi-Hsin Lo ,  Chia-Shiung Tsai ,  Lucy Chang ,  Chia-Lin Chen ,  Ming-Chih Tsai

发明人： Chih-Ta Wu ,  Jason Lee ,  Chung Chien Wang ,  Hsing-Lien Lin ,  Yu-Jen Wang ,  Yeur-Luen Tu ,  Chern-Yow Hsu ,  Yuan-Hung Liu ,  Chi-Hsin Lo ,  Chia-Shiung Tsai ,  Lucy Chang ,  Chia-Lin Chen ,  Ming-Chih Tsai

IPC分类号： H01L21/8234 ,  H01L21/8244 ,  H01L49/02 ,  H01L27/108

CPC分类号： H01L27/10814 ,  H01L27/10852 ,  H01L28/40 ,  H01L28/75

摘要： A capacitor and methods for forming the same are provided. The method includes forming a bottom electrode; treating the bottom electrode in an oxygen-containing environment to convert a top layer of the bottom electrode into a buffer layer; forming an insulating layer on the buffer layer; and forming a top electrode over the insulating layer.

摘要翻译： 提供电容器及其形成方法。 该方法包括形成底部电极; 在含氧环境中处理底部电极以将底部电极的顶层转化为缓冲层; 在缓冲层上形成绝缘层; 并在所述绝缘层上形成顶部电极。

公开(公告)号：US20070287247A1

公开(公告)日：2007-12-13

申请号：US11422701

申请日：2006-06-07

申请人： Ming-Chyi Liu ,  Chi-Hsin Lo

发明人： Ming-Chyi Liu ,  Chi-Hsin Lo

IPC分类号： H01L21/8244

CPC分类号： H01L28/60 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/76813 ,  H01L27/10852 ,  H01L27/10855

摘要： A semiconductor device with an embedded capacitor structure. A dielectric layer is disposed on a substrate, having a contact opening exposing the substrate and a trench opening above the contact opening. A first metal electrode layer is conformally disposed over the sidewalls and bottoms of the contact and trench openings. A second metal electrode layer is conformally disposed over the sidewalls and bottoms of the contact and trench openings. A capacitor dielectric layer is interposed between the first and second metal electrode layers. A method for fabricating the semiconductor device is also disclosed.

摘要翻译： 具有嵌入式电容器结构的半导体器件。 介电层设置在基板上，具有暴露基板的接触开口和接触开口上方的沟槽开口。 第一金属电极层共形地设置在触点和沟槽开口的侧壁和底部之上。 第二金属电极层共形地设置在触点和沟槽开口的侧壁和底部之上。 电容器电介质层介于第一和第二金属电极层之间。 还公开了制造半导体器件的方法。

公开(公告)号：US20070023816A1

公开(公告)日：2007-02-01

申请号：US11191437

申请日：2005-07-27

申请人： Yuan-Hung Liu ,  Shih-Chi Fu ,  Chi-Hsin Lo ,  Chia-Shiung Tsai

发明人： Yuan-Hung Liu ,  Shih-Chi Fu ,  Chi-Hsin Lo ,  Chia-Shiung Tsai

IPC分类号： H01L29/788

CPC分类号： H01L29/42324 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/7881

摘要： An EEPROM flash memory device having a floating gate electrode enabling a reduced erase voltage and method for forming the same, the floating gate electrode including an outer edge portion comprising multiple charge transfer pointed tips.

摘要翻译： 一种具有能够实现降低的擦除电压的浮动栅电极的EEPROM闪存器件及其形成方法，该浮栅电极包括包含多个电荷转移尖端的外边缘部分。

公开(公告)号：US07153755B2

公开(公告)日：2006-12-26

申请号：US11044813

申请日：2005-01-26

申请人： Shih-Chang Liu ,  Wen-Ting Chu ,  Chien-Ming Ku ,  Chi-Hsin Lo ,  Chia-Shiung Tsai ,  Chia-Ta Hsieh

发明人： Shih-Chang Liu ,  Wen-Ting Chu ,  Chien-Ming Ku ,  Chi-Hsin Lo ,  Chia-Shiung Tsai ,  Chia-Ta Hsieh

IPC分类号： H01L21/762

CPC分类号： H01L27/11521 ,  H01L21/76224 ,  H01L27/10894 ,  H01L27/11

摘要： A method is provided for fabrication of a semiconductor substrate having regions isolated from each other by shallow trench isolation (STI) structures protruding above a surface of the substrate by a step height. The method includes the steps of forming a bottom antireflective coating (BARC) layer overlying the surface of a semiconductor substrate and the surface of STI structures; etching back a portion of the BARC layer overlying at least one of the STI structures, and partially etching back the at least one of the STI structures, to reduce the step height by which the STI structure protrudes above the surface of the substrate; and removing a remaining portion of the BARC layer between adjacent STI structures. The method may be used to fabricate semiconductor devices including memory cells that have improved reliability.

摘要翻译： 提供了一种用于制造半导体衬底的方法，该半导体衬底具有通过在衬底的表面上突出台阶高度的浅沟槽隔离（STI）结构彼此隔离的区域。 该方法包括以下步骤：形成覆盖半导体衬底的表面和STI结构表面的底部抗反射涂层（BARC）层; 蚀刻覆盖所述STI结构中的至少一个的所述BARC层的一部分，并且部分地蚀刻所述STI结构中的所述至少一个，以降低所述STI结构在所述衬底的表面上方突出的台阶高度; 以及去除相邻STI结构之间的BARC层的剩余部分。 该方法可用于制造包括具有改进的可靠性的存储器单元的半导体器件。

公开(公告)号：US20050274968A1

公开(公告)日：2005-12-15

申请号：US10982978

申请日：2004-11-05

申请人： Ching-Sen Kuo ,  Feng-Jia Shiu ,  Gwo-Yuh Shiau ,  Jieh-Jang Chen ,  Shih-Chi Fu ,  Chien Tseng ,  Chia-Shiung Tsai ,  Yuan-Hung Liu ,  Yeur-Luen Tu ,  Chih-Ta Wu ,  Chi-Hsin Lo

发明人： Ching-Sen Kuo ,  Feng-Jia Shiu ,  Gwo-Yuh Shiau ,  Jieh-Jang Chen ,  Shih-Chi Fu ,  Chien Tseng ,  Chia-Shiung Tsai ,  Yuan-Hung Liu ,  Yeur-Luen Tu ,  Chih-Ta Wu ,  Chi-Hsin Lo

IPC分类号： H01L21/00 ,  H01L27/146 ,  H01L29/04 ,  H01L29/06 ,  H01L29/10 ,  H01L29/22 ,  H01L29/227 ,  H01L31/036 ,  H01L31/0376 ,  H01L31/20 ,  H01L33/00 ,  H01L47/02

CPC分类号： H01L27/14621 ,  H01L27/14625 ,  H01L27/14627 ,  H01L27/14632 ,  H01L27/14685 ,  H01L27/14687

摘要： An image sensor includes a double-microlens structure with an outer microlens aligned over an inner microlens, both microlenses aligned over a corresponding photosensor. The inner or outer microlens may be formed by a silylation process in which a reactive portion of a photoresist material reacts with a silicon-containing agent. The inner or outer microlens may be formed by step etching of a dielectric material, the step etching process including a series of alternating etch steps including an anisotropic etching step and an etching step that causes patterned photoresist to laterally recede. Subsequent isotropic etching processes may be used to smooth the etched step structure and form a smooth lens. A thermally stable and photosensitive polymeric/organic material may also be used to form permanent inner or outer lenses. The photosensitive material is coated then patterned using photolithography, reflowed, then cured to form a permanent lens structure.

摘要翻译： 图像传感器包括双微透镜结构，其外部微透镜在内部微透镜上对准，两个微透镜在相应的光电传感器上对准。 内部或外部微透镜可以通过甲硅烷基化方法形成，其中光致抗蚀剂材料的反应性部分与含硅试剂反应。 内部或外部微透镜可以通过介电材料的步骤蚀刻形成，该步骤蚀刻工艺包括一系列交替蚀刻步骤，其包括各向异性蚀刻步骤和使图案化光致抗蚀剂横向后退的蚀刻步骤。 可以使用随后的各向同性蚀刻工艺来平滑蚀刻的台阶结构并形成光滑的透镜。 热稳定和感光的聚合物/有机材料也可用于形成永久的内镜片或外镜片。 感光材料被涂覆，然后使用光刻图案化，回流，然后固化以形成永久性透镜结构。

公开(公告)号：US20050079672A1

公开(公告)日：2005-04-14

申请号：US10685127

申请日：2003-10-14

申请人： Hsiu Ouyang ,  Chi-Hsin Lo ,  Chen-Ming Huang ,  Chia-Ta Hsieh ,  Chia-Shiung Tsai

发明人： Hsiu Ouyang ,  Chi-Hsin Lo ,  Chen-Ming Huang ,  Chia-Ta Hsieh ,  Chia-Shiung Tsai

IPC分类号： H01L21/311 ,  H01L21/3213 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/115

CPC分类号： H01L27/11521 ,  H01L21/31116 ,  H01L21/32137 ,  H01L21/32138 ,  H01L21/32139 ,  H01L27/115

摘要： A split gate FET wordline electrode structure and method for forming the same including an improved polysilicon etching process including providing a semiconductor wafer process surface comprising first exposed polysilicon portions and adjacent oxide portions; forming a first oxide layer on the exposed polysilicon portions; blanket depositing a polysilicon layer on the first exposed polysilicon portions and adjacent oxide portions; forming a hardmask layer on the polysilicon layer; carrying out a multi-step reactive ion etching (RIE) process to etch through the hardmask layer and etch through a thickness portion of the polysilicon layer to form second polysilicon portions adjacent the oxide portions having upward protruding outer polysilicon fence portions; contacting the semiconductor wafer process surface with an aqueous HF solution; and, carrying out a downstream plasma etching process to remove polysilicon fence portions.

摘要翻译： 一种分裂栅FET字线电极结构及其形成方法，包括改进的多晶硅蚀刻工艺，包括提供包括第一裸露多晶硅部分和相邻氧化物部分的半导体晶片工艺表面; 在所述暴露的多晶硅部分上形成第一氧化物层; 在第一暴露的多晶硅部分和相邻的氧化物部分上覆盖多晶硅层; 在所述多晶硅层上形成硬掩模层; 执行多步反应离子蚀刻（RIE）工艺以蚀刻穿过硬掩模层并蚀刻穿过多晶硅层的厚度部分，以形成与具有向上突出的外部多晶硅栅栏部分的氧化物部分相邻的第二多晶硅部分; 使所述半导体晶片工艺表面与HF水溶液接触; 并且执行下游等离子体蚀刻工艺以去除多晶硅栅栏部分。

公开(公告)号：US06869837B1

公开(公告)日：2005-03-22

申请号：US10758316

申请日：2004-01-15

申请人： Yuan-Hung Liu ,  Yeur-Luen Tu ,  Chin-Ta Wu ,  Tsung-Hsun Huang ,  Hsiu Ouyang ,  Chi-Hsin Lo ,  Chia-Shiung Tsai

发明人： Yuan-Hung Liu ,  Yeur-Luen Tu ,  Chin-Ta Wu ,  Tsung-Hsun Huang ,  Hsiu Ouyang ,  Chi-Hsin Lo ,  Chia-Shiung Tsai

IPC分类号： H01L21/8238 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/76

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A method of fabricating word-line spacers comprising the following steps. A substrate having an inchoate split-gate flash memory structure formed thereover is provided. A conductive layer is formed over the substrate and the inchoate split-gate flash memory structure. The conductive layer having: a upper portion and lower vertical portions over the inchoate split-gate flash memory structure; and lower horizontal portions over the substrate. A dual-thickness oxide layer is formed over the conductive layer and has a greater thickness over the upper portion of the conductive layer. The oxide layer is partially etched back to remove at least the oxide layer from over the lower horizontal portions of the conductive layer to expose the underlying portions of the conductive layer. Then etching: away the exposed portions of the conductive layer over the substrate; and through at least a portion of the thinned oxide layer and into the exposed underlying portion of the conductive layer to expose a portion of the inchoate split-gate flash memory structure and to form the word-line spacers adjacent the inchoate split-gate flash memory structure.

摘要翻译： 一种制造字线间隔物的方法，包括以下步骤。 提供了具有形成在其上的初始分离栅闪存结构的衬底。 导电层形成在衬底和初生分裂栅极闪存结构之上。 所述导电层具有：上部分裂栅极闪存结构上方的上部和下部垂直部分; 并且在基底上下方水平部分。 在导电层之上形成双层氧化物层，并且在导电层的上部上具有更大的厚度。 将氧化层部分地回蚀刻以从导电层的下部水平部分上方至少去除氧化物层，以暴露导电层的下面部分。 然后蚀刻：将导电层的暴露部分远离衬底; 并且通过至少一部分减薄的氧化物层并进入导电层的暴露的下面的部分，以暴露初步分离栅闪存结构的一部分并且形成邻近先驱分离栅闪存的字线间隔物 结构体。

公开(公告)号：US6003526A

公开(公告)日：1999-12-21

申请号：US928950

申请日：1997-09-12

申请人： Chi-Hsin Lo ,  Hsing-Yuan Cheu

发明人： Chi-Hsin Lo ,  Hsing-Yuan Cheu

IPC分类号： H01J37/32 ,  H01L21/00 ,  B08B5/00

CPC分类号： H01L21/67028 ,  H01J37/32862

摘要： A method for cleaning a plasma etch chamber is described which can be carried out by first terminating an etch process by stopping a process gas flow into the chamber, then maintaining a RF power in the etch chamber, and flowing a cleaning gas consists of at least one inert gas and oxygen through the chamber at a flow rate higher than the flow rate for the process gas for a length of time sufficient to evacuate substantially all the contaminating byproducts formed by the process gas. A suitable cleaning gas contains at least one inert gas of Ar, He, or N.sub.2 mixed with O.sub.2. A sufficient length of time for the cleaning process is at least 5 seconds, and preferably at least 10 seconds.

摘要翻译： 描述了用于清洁等离子体蚀刻室的方法，其可以通过首先通过停止工艺气体流入室中终止蚀刻工艺，然后在蚀刻室中保持RF功率，并且清洁气体的流动至少由 一个惰性气体和氧气通过腔室，流速高于处理气体的流速足以将基本上所有由工艺气体形成的污染副产物抽空的时间。 合适的清洁气体含有与O2混合的至少一种Ar，He或N 2的惰性气体。 清洁过程的足够长的时间是至少5秒，优选至少10秒。

公开(公告)号：US5755891A

公开(公告)日：1998-05-26

申请号：US789214

申请日：1997-01-24

申请人： Chi-Hsin Lo ,  Dowson Jang ,  Hsueh-Liang Chiu

发明人： Chi-Hsin Lo ,  Dowson Jang ,  Hsueh-Liang Chiu

IPC分类号： B08B7/00 ,  B08B6/00 ,  H01L21/302

CPC分类号： B08B7/0035

摘要： An improved process is described for the post-etching treatment after subtractive etching of aluminum and aluminum-alloy layers in the fabrication of semiconductor integrated circuit devices. The improvement consists of in situ exposure immediately after subtractive etching of the metal pattern to a reactive plasma sustained in a mixture of oxygen and carbon tetrafluoride gases by continuous radiofrequency power input for a controlled period of time.

摘要翻译： 对在半导体集成电路器件的制造中对铝和铝合金层进行减蚀蚀后的后蚀刻处理进行了描述。 该改进包括在通过连续的射频功率输入在受控时间段内将金属图案减去蚀刻到氧气和四氟化碳气体的混合物中的反应性等离子体之后立即曝光。

公开(公告)号：US08227850B2

公开(公告)日：2012-07-24

申请号：US12723381

申请日：2010-03-12

申请人： Shih-Chang Liu ,  Ming-Hui Shen ,  Chi-Hsin Lo ,  Chia-Shiung Tsai ,  Yi-Shin Chu

发明人： Shih-Chang Liu ,  Ming-Hui Shen ,  Chi-Hsin Lo ,  Chia-Shiung Tsai ,  Yi-Shin Chu

IPC分类号： H01L29/76

CPC分类号： H01L29/7881 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/513 ,  H01L29/6656 ,  Y10S438/945

摘要： A method for fabricating a gated semiconductor device, and the device resulting from performing the method. In a preferred embodiment, the method includes forming a hard mask for use in gate formation on one or more layers of alternately insulating and conducting material that have been formed on a substrate. The hard mask preferably includes three layers; a lower nitride layer, a middle oxide, and an upper nitride layer. In this embodiment, the middle oxide layer is formed with the rest of the hard mask, and then reduced in a lateral dimension, preferably using a DHF dip. A dielectric layer formed over the gate structure, including the hard mask, then etched back, self-aligns to be reduced-dimension oxide layer. In addition, where two conducting, that is gate layers are present, the lower layer is laterally reduced in dimension on at least one side to create an undercut.

摘要翻译： 一种用于制造门控半导体器件的方法，以及由执行该方法产生的器件。 在一个优选实施例中，该方法包括形成用于在基板上形成的交替绝缘和导电材料的一层或多层上形成栅极的硬掩模。 硬掩模优选包括三层; 下氮化物层，中间氧化物和上氮化物层。 在该实施例中，中间氧化物层与硬掩模的其余部分形成，然后以侧向尺寸减小，优选使用DHF浸渍。 形成在栅极结构上方的电介质层，包括硬掩模，然后被回蚀，自对准成为尺寸减小的氧化物层。 此外，当存在两个导电（即栅极层）时，下层在至少一侧的横向尺寸上横向减小以产生底切。