公开(公告)号：US20090294806A1

公开(公告)日：2009-12-03

申请号：US12128996

申请日：2008-05-29

申请人： Zhong DONG ,  Ching-Hwa CHEN

发明人： Zhong DONG ,  Ching-Hwa CHEN

IPC分类号： H01L29/78 ,  H01L21/322

CPC分类号： H01L21/324 ,  H01L21/28167 ,  H01L21/28238 ,  H01L29/78

摘要： Performance of field effect transistors and other channel dependent devices formed on a monocrystalline substrate is improved by carrying out a high temperature anneal in a nitrogen releasing atmosphere while the substrate is coated by a sacrificial oxide coating containing easily diffusible atoms that can form negatively charged ions and can diffuse deep into the substrate. In one embodiment, the easily diffusible atoms comprise at least 5% by atomic concentration of chlorine atoms in the sacrificial oxide coating and the nitrogen releasing atmosphere includes NO. The high temperature anneal is carried out for less than 10 hours at a temperature less than 1100° C.

摘要翻译： 通过在氮气释放气氛中进行高温退火，同时通过包含容易扩散的原子的牺牲氧化物涂层涂覆基底，从而改善在单晶衬底上形成的场效应晶体管和其它通道相关器件的性能，所述牺牲氧化物涂层可形成带负电荷的离子， 可以深层扩散到底物中。 在一个实施方案中，容易扩散的原子在牺牲氧化物涂层中包含至少5％的原子浓度的氯原子，并且氮气释放气氛包括NO。 高温退火在低于1100℃的温度下进行少于10小时。

公开(公告)号：US07297597B2

公开(公告)日：2007-11-20

申请号：US10898273

申请日：2004-07-23

申请人： Zhong Dong ,  Chuck Jang ,  Ching-Hwa Chen ,  Chia-Shun Hsiao

发明人： Zhong Dong ,  Chuck Jang ,  Ching-Hwa Chen ,  Chia-Shun Hsiao

IPC分类号： H01L21/336

CPC分类号： H01L27/11526 ,  H01L21/28273 ,  H01L27/105 ,  H01L27/11546 ,  H01L29/42324

摘要： Conventional fabrication of top oxide in an ONO-type memory cell stack usually produces Bird's Beak. Certain materials in the stack such as silicon nitrides are relatively difficult to oxidize. As a result oxidation does not proceed uniformly along the multi-layered height of the ONO-type stack. The present disclosure shows how radical-based fabrication of top-oxide of an ONO stack (i.e. by ISSG method) can help to reduce formation of Bird's Beak. More specifically, it is indicated that short-lived oxidizing agents (e.g., atomic oxygen) are able to better oxidize difficult to oxidize materials such as silicon nitride and the it is indicated that the short-lived oxidizing agents alternatively or additionally do not diffuse deeply through already oxidized layers of the ONO stack such as the lower silicon oxide layer. As a result, a more uniform top oxide dielectric can be fabricated with more uniform breakdown voltages along its height. Additionally, adjacent low and high voltage transistors may benefit from simultaneous formation of their gate dielectrics with use of the radical-based oxidizing method.

摘要翻译： ONO型记忆体堆叠中的顶层氧化物的常规制造通常产生Bird's Beak。 叠层中的某些材料如氮化硅相对难以氧化。 因此，氧化不会沿着ONO型堆叠的多层高度均匀地进行。 本公开显示了如何基于根基的ONO堆叠的顶部氧化物的制造（即通过ISSG方法）可以帮助减少Bird's Beak的形成。 更具体地，表明短寿命氧化剂（例如原子氧）能够更好地氧化难以氧化的材料，例如氮化硅，并且表明短寿命氧化剂交替地或另外不会扩散深 通过已经氧化的ONO堆叠层，例如较低的氧化硅层。 结果，可以制造更均匀的顶部氧化物电介质，沿其高度具有更均匀的击穿电压。 此外，相邻的低压和高压晶体管可以受益于使用基于自由基的氧化方法同时形成其栅极电介质。

公开(公告)号：US20070207627A1

公开(公告)日：2007-09-06

申请号：US11365013

申请日：2006-03-01

申请人： Zhong Dong ,  Chiliang Chen ,  Ching-Hwa Chen

发明人： Zhong Dong ,  Chiliang Chen ,  Ching-Hwa Chen

IPC分类号： H01L21/31

CPC分类号： H01L29/0847 ,  H01L21/28202 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11536 ,  H01L27/11546 ,  H01L29/7881

摘要： In-situ steam generation (ISSG) is used to reduce the nitrogen concentration in silicon and silicon oxide areas.

摘要翻译： 原位蒸汽发生（ISSG）用于降低硅和氧化硅区域的氮浓度。

公开(公告)号：US06221792B1

公开(公告)日：2001-04-24

申请号：US08881710

申请日：1997-06-24

申请人： Yun-Yen Jack Yang ,  Ching-Hwa Chen ,  Yea-Jer Arthur Chen

发明人： Yun-Yen Jack Yang ,  Ching-Hwa Chen ,  Yea-Jer Arthur Chen

IPC分类号： H01L2144

CPC分类号： H01L21/76856 ,  H01L21/76843

摘要： A nitridization process to form a barrier layer on a substrate is described. The nitridization process includes depositing a layer of metal or metal silicide on a surface of the substrate, placing the substrate into a high density, low pressure plasma reactor, introducing into the high density low pressure plasma reactor a gas including nitrogen, and striking a plasma in the high density, low pressure plasma reactor under conditions that promote nitridization of at least a portion of the layer of metal or metal silicide to produce a composition of metal nitride or metal silicon nitride, respectively.

摘要翻译： 描述了在衬底上形成阻挡层的氮化工艺。 氮化工艺包括在衬底的表面上沉积金属或金属硅化物层，将衬底放置在高密度，低压等离子体反应器中，将包含氮气的气体引入高密度低压等离子体反应器中， 在高密度低压等离子体反应器中，在促进至少一部分金属或金属硅化物层的氮化的条件下，分别产生金属氮化物或金属氮化硅的组合物。

公开(公告)号：US5824605A

公开(公告)日：1998-10-20

申请号：US509080

申请日：1995-07-31

申请人： Ching-Hwa Chen ,  David Liu ,  Mark J. Christensen

发明人： Ching-Hwa Chen ,  David Liu ,  Mark J. Christensen

IPC分类号： H01J37/32 ,  H05H1/46 ,  H05H1/00

CPC分类号： H01J37/3244 ,  H01J37/321 ,  H05H1/46

摘要： A gas dispersion window for a plasma etching or plasma deposition reactor including a housing having a chamber in which an article can be treated with plasma. The housing includes at least one inlet port connected to an interior of the chamber through which process gas can be supplied to the chamber. A radiofrequency energy source is arranged to pass radiofrequency energy into the chamber and induce plasma in the interior of the chamber by activating, with an electric field induced by the radiofrequency energy source, process gas supplied to the chamber through the inlet port. A dielectric window formed by spaced apart first and second dielectric members has an inner surface thereof forming part of an inner wall of the chamber. Radiofrequency energy passes from the radiofrequency energy source to the interior of the chamber through the dielectric window. The process gas is supplied to the gap between the first and second dielectric members and passes inwardly into the chamber through gas dispersion holes in the second member.

摘要翻译： 一种用于等离子体蚀刻或等离子体沉积反应器的气体分散窗，其包括具有腔室的壳体，其中可以用等离子体处理制品。 壳体包括连接到室的内部的至少一个入口端口，通过该入口端口可将工艺气体供应到室。 射频能源设置成将射频能量传递到腔室中并且通过由射频能量源引起的电场通过入口端口供应到腔室的处理气体进行激活而在腔室的内部引起等离子体。 由间隔开的第一和第二电介质构件形成的电介质窗口具有形成室的内壁的一部分的内表面。 射频能量通过电介质窗从射频能量传递到腔室的内部。 工艺气体被供应到第一和第二电介质构件之间的间隙，并通过第二构件中的气体分散孔向内进入腔室。

公开(公告)号：US5812361A

公开(公告)日：1998-09-22

申请号：US624988

申请日：1996-03-29

申请人： Phillip Lawrence Jones ,  Seyed Jafar Jafarian-Tehrani ,  Boris V. Atlas ,  David R-Chen Liu ,  Ken Edward Tokunaga ,  Ching-Hwa Chen

发明人： Phillip Lawrence Jones ,  Seyed Jafar Jafarian-Tehrani ,  Boris V. Atlas ,  David R-Chen Liu ,  Ken Edward Tokunaga ,  Ching-Hwa Chen

IPC分类号： H01L21/68 ,  B25J15/06 ,  H01L21/683 ,  H02N13/00

CPC分类号： H01L21/6833 ,  Y10T279/23

摘要： An electrostatic chuck system having an electrostatic chuck for securely holding a wafer on a surface of the electrostatic chuck. The electrostatic chuck system comprises a wafer bias sensor coupled to a first portion of the electrostatic chuck for sensing an alternating current signal at the first portion. The wafer bias sensor outputs, responsive to the alternating current signal, a direct current voltage level representative of a direct current bias level of the wafer. The electrostatic chuck system further comprises a variable electrostatic chuck power supply coupled to the wafer bias sensor. The variable electrostatic chuck power supply provides a first potential level to the first portion of the electrostatic chuck. The first potential level is modified, responsive to the direct current voltage level, to substantially maintain a first predefined potential difference between the first portion of the electrostatic chuck and a first region of the wafer overlaying the first portion irrespective of a magnitude of the direct current bias level of the wafer.

摘要翻译： 一种具有用于将晶片牢固地保持在静电卡盘的表面上的静电卡盘的静电卡盘系统。 静电吸盘系统包括耦合到静电卡盘的第一部分的晶片偏置传感器，用于感测第一部分处的交流信号。 晶片偏置传感器响应于交流信号输出代表晶片的直流偏置电平的直流电压电平。 静电卡盘系统还包括耦合到晶片偏置传感器的可变静电卡盘电源。 可变静电卡盘电源为静电卡盘的第一部分提供第一电位电平。 响应于直流电压电平修改第一电位电平，以基本上保持静电卡盘的第一部分和覆盖第一部分的晶片的第一区域之间的第一预定电位差，而不管直流电流的大小 晶片的偏置电平。

公开(公告)号：US5368710A

公开(公告)日：1994-11-29

申请号：US038612

申请日：1993-03-29

申请人： Ching-Hwa Chen ,  David Liu ,  Duc Tran

发明人： Ching-Hwa Chen ,  David Liu ,  Duc Tran

IPC分类号： H05H1/46 ,  C23C16/50 ,  C23C16/507 ,  C23F4/00 ,  H01J37/32 ,  H01L21/205 ,  H01L21/302 ,  H01L21/3065 ,  C23C14/00

CPC分类号： H01J37/32238 ,  C23C16/507 ,  H01J37/32082 ,  H01J37/321

摘要： A method of plasma treating an article in a housing having a chamber in which the article such as a wafer can be treated with plasma. The housing includes at least one inlet port connected to an interior of the chamber through which process gas can be supplied to the chamber. A radiofrequency energy source is arranged to pass radiofrequency energy into the chamber and induce plasma in the interior of the chamber by activating, with an electric field induced by the radiofrequency energy source, process gas supplied to the chamber through the inlet port. A dielectric window having an inner surface thereof forms part of an inner wall of the chamber. Radiofrequency energy passes from the radiofrequency energy source to the interior of the chamber through the dielectric window. The dielectric window has a thickness which varies at different points along the inner surface thereof such that the thickness is largest at a central portion of the dielectric window. The dielectric window is effective to decrease the induced electric field in the interior of the chamber near the central portion of the dielectric window.

摘要翻译： 一种等离子体处理具有室的壳体中的物品的方法，其中诸如晶片的物品可以用等离子体处理。 壳体包括连接到室的内部的至少一个入口端口，通过该入口端口可将工艺气体供应到室。 射频能源设置成将射频能量传递到腔室中并且通过由射频能量源引起的电场通过入口端口供应到腔室的处理气体进行激活而在腔室的内部引起等离子体。 具有内表面的电介质窗形成室的内壁的一部分。 射频能量通过电介质窗从射频能量传递到腔室的内部。 电介质窗口具有在其内表面的不同点处变化的厚度，使得在电介质窗口的中心部分处的厚度最大。 电介质窗口有效地减小在电介质窗口的中心部分附近的室内的感应电场。

公开(公告)号：US4897887A

公开(公告)日：1990-02-06

申请号：US238731

申请日：1988-08-31

申请人： Jiann-Jong Chen ,  Ching-Hwa Chen

发明人： Jiann-Jong Chen ,  Ching-Hwa Chen

IPC分类号： A41D25/02

CPC分类号： A41D25/008 ,  A41D25/02 ,  A41D25/025

摘要： A preknotted adjustable necktie comprises a knot former having, an inner body (62) and an outer body (61), an inner tie member with a zipper (3), an outer tie member (5), and a rivet (63). The knot former serves forming and control functions, and the inner tie member is sandwiched between the inner and outer bodies thereof, with a pulling button of the zipper slider on the inner tie member secured to the inner and outer bodies of the knot former and to the outer tie member by a rivet. The outer tie member is tied into a fixed knot over the knot former. By means of the presence of a pair of leaf springs (622) on the inner body, the position of the tie knot and the zipper slider can be adjusted freely and retained in the position set.

摘要翻译： 一个预打结的可调节领带包括具有内部主体（62）和外部主体（61），具有拉链（3），内部连接件（5）和铆钉（63）的内部连接件的结形成器。 该结成型器具有成形和控制功能，并且内部连接件夹在其内部和外部本体之间，并且内部连接件上的拉链滑块的拉动件固定到打结机的内部和外部主体上，并且 外部绑带构件由铆钉。 外部连接构件被绑在结上的固定结。 通过在内体上存在一对板簧（622），可以自由地调节扎结和拉链滑块的位置并保持在所设定的位置。

公开(公告)号：US20100047994A1

公开(公告)日：2010-02-25

申请号：US12196067

申请日：2008-08-21

申请人： Zhong Dong ,  Ching-Hwa Chen

发明人： Zhong Dong ,  Ching-Hwa Chen

IPC分类号： H01L21/764

CPC分类号： H01L21/76224 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881 ,  H01L29/792

摘要： After forming a stack of layers (130, 140, 310) for a transistor or a charge-trapping memory over an active area (110), and before etching isolation trenches (160) in the semiconductor substrate (120) with the stack as a mask, spacers (610) are formed on the stack's sidewalls. The trench etch may include a lateral component, so the top edges of the trenches may be laterally recessed to a position under the spacers or the stack. After the etch, the spacers are removed to facilitate filling the trenches with the dielectric (to eliminate voids at the recessed top edges of the trenches). Other embodiments are also provided.

摘要翻译： 在有源区（110）上形成用于晶体管或电荷俘获存储器的层叠层（130,140,​​310）之后，以及在将堆叠中的隔离沟槽（160）刻蚀为半导体衬底 掩模，间隔物（610）形成在堆叠的侧壁上。 沟槽蚀刻可以包括侧向部件，因此沟槽的顶部边缘可以横向凹入到间隔件或堆叠下的位置。 在蚀刻之后，去除间隔物以便于用电介质填充沟槽（以消除沟槽凹陷的顶部边缘处的空隙）。 还提供了其他实施例。

公开(公告)号：US20090096009A1

公开(公告)日：2009-04-16

申请号：US11872998

申请日：2007-10-16

申请人： Zhong Dong ,  Chiliang Chen ,  Ching-Hwa Chen

发明人： Zhong Dong ,  Chiliang Chen ,  Ching-Hwa Chen

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L29/7883 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/7885 ,  H01L29/792

摘要： A nonvolatile memory cell stores at least 50% of the charge in a dielectric, charge-trapping layer (160) and at least 20% of the charge in a floating gate (170). The floating gate is at most 20 nm thick.

摘要翻译： 非易失性存储单元将电荷的至少50％存储在电介质电荷俘获层（160）中，并且在浮动栅极（170）中存储至少20％的电荷。 浮栅最多为20nm厚。