公开(公告)号：US06221792B1

公开(公告)日：2001-04-24

申请号：US08881710

申请日：1997-06-24

申请人： Yun-Yen Jack Yang ,  Ching-Hwa Chen ,  Yea-Jer Arthur Chen

发明人： Yun-Yen Jack Yang ,  Ching-Hwa Chen ,  Yea-Jer Arthur Chen

IPC分类号： H01L2144

CPC分类号： H01L21/76856 ,  H01L21/76843

摘要： A nitridization process to form a barrier layer on a substrate is described. The nitridization process includes depositing a layer of metal or metal silicide on a surface of the substrate, placing the substrate into a high density, low pressure plasma reactor, introducing into the high density low pressure plasma reactor a gas including nitrogen, and striking a plasma in the high density, low pressure plasma reactor under conditions that promote nitridization of at least a portion of the layer of metal or metal silicide to produce a composition of metal nitride or metal silicon nitride, respectively.

摘要翻译： 描述了在衬底上形成阻挡层的氮化工艺。 氮化工艺包括在衬底的表面上沉积金属或金属硅化物层，将衬底放置在高密度，低压等离子体反应器中，将包含氮气的气体引入高密度低压等离子体反应器中， 在高密度低压等离子体反应器中，在促进至少一部分金属或金属硅化物层的氮化的条件下，分别产生金属氮化物或金属氮化硅的组合物。

公开(公告)号：US07851339B2

公开(公告)日：2010-12-14

申请号：US12128996

申请日：2008-05-29

申请人： Zhong Dong ,  Ching-Hwa Chen

发明人： Zhong Dong ,  Ching-Hwa Chen

IPC分类号： H01L21/225

CPC分类号： H01L21/324 ,  H01L21/28167 ,  H01L21/28238 ,  H01L29/78

摘要： Performance of field effect transistors and other channel dependent devices formed on a monocrystalline substrate is improved by carrying out a high temperature anneal in a nitrogen releasing atmosphere while the substrate is coated by a sacrificial oxide coating containing easily diffusible atoms that can form negatively charged ions and can diffuse deep into the substrate. In one embodiment, the easily diffusible atoms comprise at least 5% by atomic concentration of chlorine atoms in the sacrificial oxide coating and the nitrogen releasing atmosphere includes NO. The high temperature anneal is carried out for less than 10 hours at a temperature less than 1100° C.

摘要翻译： 通过在氮气释放气氛中进行高温退火，同时通过包含容易扩散的原子的牺牲氧化物涂层涂覆基底，从而改善在单晶衬底上形成的场效应晶体管和其它通道相关器件的性能，所述牺牲氧化物涂层可形成带负电荷的离子， 可以深层扩散到底物中。 在一个实施方案中，容易扩散的原子在牺牲氧化物涂层中包含至少5％的原子浓度的氯原子，并且氮气释放气氛包括NO。 高温退火在低于1100℃的温度下进行少于10小时。

公开(公告)号：US20090032861A1

公开(公告)日：2009-02-05

申请号：US11830524

申请日：2007-07-30

申请人： Zhong Dong ,  Chiliang Chen ,  Ching-Hwa Chen

发明人： Zhong Dong ,  Chiliang Chen ,  Ching-Hwa Chen

IPC分类号： H01L29/792 ,  H01L21/3205

CPC分类号： H01L29/42332 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/42348

摘要： A nonvolatile memory has a charge trapping layer which includes a layer (130) made of silicon nitride doped with germanium or phosphorus (210). The germanium or phosphorus contains a large percentage of scattered, non-crystallized atoms uniformly distributed in the silicon nitride layer to increase the charge trapping density.

摘要翻译： 非易失性存储器具有电荷捕获层，其包含掺杂有锗或磷的氮化硅（210）制成的层（130）。 锗或磷含有大量的均匀分布在氮化硅层中的散射的非结晶原子，以增加电荷捕获密度。

公开(公告)号：US06337277B1

公开(公告)日：2002-01-08

申请号：US09606842

申请日：2000-06-28

申请人： Wen-Ben Chou ,  Rajinder Dhindsa ,  Ching-Hwa Chen

发明人： Wen-Ben Chou ,  Rajinder Dhindsa ,  Ching-Hwa Chen

IPC分类号： H01L21302

CPC分类号： H01L21/31138

摘要： A method of cleanly etching an organic polymer layer disposed over a substrate is disclosed. The invention is particularly useful in damascene processing where openings are etched in the organic polymer layer to form interconnects. The method includes lowering the temperature of the substrate. The method also includes flowing H2O vapor over the organic polymer layer and condensing (or freezing) the H2O vapor on the organic polymer layer. The method additionally includes etching through the organic polymer layer and the condensed H2O vapor to form an opening having a side wall. The condensed (or frozen) H2O vapor is arranged to form a passivating film (of ice) along the side wall of the opening to protect the side wall from etching.

摘要翻译： 公开了一种干净地蚀刻位于衬底上的有机聚合物层的方法。 本发明特别适用于在有机聚合物层中蚀刻开口以形成互连的镶嵌加工中。 该方法包括降低基板的温度。 该方法还包括将H 2 O蒸气流过有机聚合物层并将H 2 O蒸气冷凝（或冷冻）在有机聚合物层上。 该方法还包括通过有机聚合物层和冷凝的H 2 O蒸气蚀刻以形成具有侧壁的开口。 冷凝（或冷冻的）H 2 O蒸气被布置成沿着开口的侧壁形成钝化膜（冰），以保护侧壁免受蚀刻。

公开(公告)号：US07807577B2

公开(公告)日：2010-10-05

申请号：US12196067

申请日：2008-08-21

申请人： Zhong Dong ,  Ching-Hwa Chen

发明人： Zhong Dong ,  Ching-Hwa Chen

IPC分类号： H01L21/311

CPC分类号： H01L21/76224 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881 ,  H01L29/792

摘要： After forming a stack of layers (130, 140, 310) for a transistor or a charge-trapping memory over an active area (110), and before etching isolation trenches (160) in the semiconductor substrate (120) with the stack as a mask, spacers (610) are formed on the stack's sidewalls. The trench etch may include a lateral component, so the top edges of the trenches may be laterally recessed to a position under the spacers or the stack. After the etch, the spacers are removed to facilitate filling the trenches with the dielectric (to eliminate voids at the recessed top edges of the trenches). Other embodiments are also provided.

摘要翻译： 在有源区（110）上形成用于晶体管或电荷俘获存储器的层叠层（130,140,​​310）之后，以及在将堆叠中的隔离沟槽（160）刻蚀为半导体衬底 掩模，间隔物（610）形成在堆叠的侧壁上。 沟槽蚀刻可以包括侧向部件，因此沟槽的顶部边缘可以横向凹入到间隔件或堆叠下的位置。 在蚀刻之后，去除间隔物以便于用电介质填充沟槽（以消除沟槽的凹陷顶部边缘处的空隙）。 还提供了其他实施例。

公开(公告)号：US20100068658A1

公开(公告)日：2010-03-18

申请号：US12233298

申请日：2008-09-18

申请人： Fenghong Zhang ,  Jian Xu ,  Xinyu Zhang ,  Ching-Hwa Chen ,  Leu Mei

发明人： Fenghong Zhang ,  Jian Xu ,  Xinyu Zhang ,  Ching-Hwa Chen ,  Leu Mei

IPC分类号： G03F7/20

CPC分类号： G03F1/00 ,  G03F7/70558

摘要： A pillar array is printed in positive photoresist using an optical mask (108) having an array of features (310) corresponding to the pillars. The pillars' width/length dimensions are below the exposure wavelength. Superior results can be achieved (less peeling off of the pillars and less overexposure at the center of each pillar) if the mask features (310) are downsized relative to the pillars' target sizes, and the exposure energy is reduced. Negative photoresist (with a dark field mask) can be used, and can provide good results (in terms of pillars peeling-off) if the combined area of the features (410) corresponding to the pillars is smaller than the area between the features (410).

摘要翻译： 使用具有对应于柱的特征阵列（310）的光学掩模（108）将柱阵列印刷在正性光致抗蚀剂中。 支柱的宽度/长度尺寸低于曝光波长。 如果掩模特征（310）相对于柱体的目标尺寸减小，并且曝光能量减小，则可以实现优异的结果（较少的柱的剥离和在每个柱的中心处较少的过度曝光）。 如果与柱相对应的特征（410）的组合面积小于特征之间的面积，则可以使用负光致抗蚀剂（具有暗场掩模），并且可以提供良好的结果（在柱子剥离方面） 410）。

公开(公告)号：US20060017092A1

公开(公告)日：2006-01-26

申请号：US10898273

申请日：2004-07-23

申请人： Zhong Dong ,  Chuck Jang ,  Ching-Hwa Chen ,  Chia-Shun Hsiao

发明人： Zhong Dong ,  Chuck Jang ,  Ching-Hwa Chen ,  Chia-Shun Hsiao

IPC分类号： H01L21/8242 ,  H01L21/336

CPC分类号： H01L27/11526 ,  H01L21/28273 ,  H01L27/105 ,  H01L27/11546 ,  H01L29/42324

摘要： Conventional fabrication of top oxide in an ONO-type memory cell stack usually produces Bird's Beak. Certain materials in the stack such as silicon nitrides are relatively difficult to oxidize. As a result oxidation does not proceed uniformly along the multi-layered height of the ONO-type stack. The present disclosure shows how radical-based fabrication of top-oxide of an ONO stack (i.e. by ISSG method) can help to reduce formation of Bird's Beak. More specifically, it is indicated that short-lived oxidizing agents (e.g., atomic oxygen) are able to better oxidize difficult to oxidize materials such as silicon nitride and the it is indicated that the short-lived oxidizing agents alternatively or additionally do not diffuse deeply through already oxidized layers of the ONO stack such as the lower silicon oxide layer. As a result, a more uniform top oxide dielectric can be fabricated with more uniform breakdown voltages along its height. Additionally, adjacent low and high voltage transistors may benefit from simultaneous formation of their gate dielectrics with use of the radical-based oxidizing method.

摘要翻译： ONO型记忆体堆叠中的顶层氧化物的常规制造通常产生Bird's Beak。 叠层中的某些材料如氮化硅相对难以氧化。 因此，氧化不会沿着ONO型堆叠的多层高度均匀地进行。 本公开显示了如何基于根基的ONO堆叠的顶部氧化物的制造（即通过ISSG方法）可以帮助减少Bird's Beak的形成。 更具体地，表明短寿命氧化剂（例如原子氧）能够更好地氧化难以氧化的材料，例如氮化硅，并且表明短寿命氧化剂交替地或另外不会扩散深 通过已经氧化的ONO堆叠层，例如较低的氧化硅层。 结果，可以制造更均匀的顶部氧化物电介质，沿其高度具有更均匀的击穿电压。 此外，相邻的低压和高压晶体管可以受益于使用基于自由基的氧化方法同时形成其栅极电介质。

公开(公告)号：US20050227437A1

公开(公告)日：2005-10-13

申请号：US10821100

申请日：2004-04-07

申请人： Zhong Dong ,  Chuck Jang ,  Ching-Hwa Chen ,  Chunchieh Huang ,  Jin-Ho Kim ,  Vei-Han Chan ,  Chung Leung ,  Chia-Shun Hsiao ,  George Kovall ,  Steven Yang

发明人： Zhong Dong ,  Chuck Jang ,  Ching-Hwa Chen ,  Chunchieh Huang ,  Jin-Ho Kim ,  Vei-Han Chan ,  Chung Leung ,  Chia-Shun Hsiao ,  George Kovall ,  Steven Yang

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L29/51 ,  H01L29/788

CPC分类号： H01L21/28273 ,  H01L29/42328 ,  H01L29/513 ,  H01L29/7881

摘要： Conventional fabrication of sidewall oxide around an ONO-type memory cell stack usually produces Bird's Beak because prior to the fabrication, there is an exposed sidewall of the ONO-type memory cell stack that exposes side parts of a plurality of material layers respectively composed of different materials. Certain materials in the stack such as silicon nitrides are more difficult to oxidize than other materials in the stack such polysilicon. As a result oxidation does not proceed uniformly along the multi-layered height of the sidewall. The present disclosure shows how radical-based fabrication of sidewall dielectric can help to reduce the Bird's Beak formation. More specifically, it is indicated that short-lived oxidizing agents (e.g., atomic oxygen) are able to better oxidize difficult to oxidize materials such as silicon nitride and the it is indicated that the short-lived oxidizing agents alternatively or additionally do not diffuse as deeply through already oxidized layers of the sidewall such as silicon oxide layers. As a result, a more uniform sidewall dielectric can be fabricated with more uniform breakdown voltages along it height.

摘要翻译： 通常在ONO型存储单元堆叠周围制造侧壁氧化物通常产生鸟喙，因为在制造之前，存在ONO型存储单元堆叠的暴露的侧壁，其暴露分别由不同的多个材料层组成的多个材料层的侧面部分 材料 堆叠中的某些材料如氮化硅比堆叠中的其它材料更难以氧化，这样的多晶硅。 结果，氧化不沿着侧壁的多层高度均匀地进行。 本公开显示了基于侧壁电介质的基于基础的制造有助于减少鸟喙形成。 更具体地，表明短寿命氧化剂（例如原子氧）能够更好地氧化难以氧化的材料如氮化硅，并且表明短寿命氧化剂交替地或另外不扩散为 深深地通过侧壁的已氧化层，例如氧化硅层。 结果，可以制造更均匀的侧壁电介质，沿其高度具有更均匀的击穿电压。

公开(公告)号：US4835794A

公开(公告)日：1989-06-06

申请号：US163592

申请日：1988-03-03

申请人： Jiann-Jong Chen ,  Ching-Hwa Chen

发明人： Jiann-Jong Chen ,  Ching-Hwa Chen

IPC分类号： A41D25/02 ,  A44B19/30

CPC分类号： A41D25/008 ,  A41D25/02 ,  A44B19/303 ,  Y10T24/2566

摘要： A novel preset necktie comprises an outer tie, and inner tie, a zipper, a zipper slider of unique configuration, and a support body. The outer and the inner ties are both separate individual bodies with the upper portion of the inner tie being connected to form a loop and a zipper being disposed to the inner side of the lower portion thereof to form into the tie loop. With the inner tie having been threaded through the support body and the pull tab of the specially designed slider secured to the inner side of said slider, the size of the tie loop can be adjusted by pushing or pulling said support body. A pressing spring plate is provided on the inner side of the slider so as to keep the shape of the tie loop fixed. The upper portion of the outer tie is secured to the support body by means of a rivet and preset into a regular knot such that the user does not have to set the knot each time when wearing then necktie.

摘要翻译： 一个新颖的预制领带包括一个外部领带，内部领带，拉链，独特构造的拉链滑块和支撑体。 外部和内部连接件是分开的单个主体，内部连接件的上部连接以形成一个环，并且拉链设置在其下部的内侧以形成连接环。 由于内部连接件已经穿过支撑体，并且特别设计的滑块的拉片固定到所述滑块的内侧，可以通过推动或拉动所述支撑体来调节连接环的尺寸。 在滑块的内侧设置有按压弹簧板，以使扎带的形状保持固定。 外部系带的上部通过铆钉固定到支撑体上，并预先设置成规则的结，使得用户每次穿着领带时都不必设置结。

公开(公告)号：US20100047994A1

公开(公告)日：2010-02-25

申请号：US12196067

申请日：2008-08-21

申请人： Zhong Dong ,  Ching-Hwa Chen

发明人： Zhong Dong ,  Ching-Hwa Chen

IPC分类号： H01L21/764

CPC分类号： H01L21/76224 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881 ,  H01L29/792

摘要： After forming a stack of layers (130, 140, 310) for a transistor or a charge-trapping memory over an active area (110), and before etching isolation trenches (160) in the semiconductor substrate (120) with the stack as a mask, spacers (610) are formed on the stack's sidewalls. The trench etch may include a lateral component, so the top edges of the trenches may be laterally recessed to a position under the spacers or the stack. After the etch, the spacers are removed to facilitate filling the trenches with the dielectric (to eliminate voids at the recessed top edges of the trenches). Other embodiments are also provided.

摘要翻译： 在有源区（110）上形成用于晶体管或电荷俘获存储器的层叠层（130,140,​​310）之后，以及在将堆叠中的隔离沟槽（160）刻蚀为半导体衬底 掩模，间隔物（610）形成在堆叠的侧壁上。 沟槽蚀刻可以包括侧向部件，因此沟槽的顶部边缘可以横向凹入到间隔件或堆叠下的位置。 在蚀刻之后，去除间隔物以便于用电介质填充沟槽（以消除沟槽凹陷的顶部边缘处的空隙）。 还提供了其他实施例。