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    Nonvolatile memory devices and method of manufacturing the same
    2.
    发明授权
    Nonvolatile memory devices and method of manufacturing the same 有权
    非易失性存储器件及其制造方法

    公开(公告)号：US07956343B2

    公开(公告)日：2011-06-07

    申请号：US12010921

    申请日：2008-01-31

    Applicant: Yong-wook Kwon ,  Chul-soon Kwon ,  Young-cheon Jeong

    Inventor： Yong-wook Kwon ,  Chul-soon Kwon ,  Young-cheon Jeong

    IPC: H01L47/00

    CPC classification number: H01L27/24 ,  G11C13/0004 ,  G11C2213/79

    Abstract: Example embodiments provide a nonvolatile memory device using resistive elements. The nonvolatile memory device may include a semiconductor substrate, a plurality of variable resistance patterns on the semiconductor substrate, and a plurality of heat sink patterns that are level with the variable resistance patterns and coupled to a ground voltage.

    Abstract translation: 示例性实施例提供了使用电阻元件的非易失性存储器件。 非易失性存储器件可以包括半导体衬底，半导体衬底上的多个可变电阻图案以及与可变电阻图案相平行并耦合到接地电压的多个散热器图案。

    Method of fabricating nonvolatile memory device
    3.
    发明授权
    Method of fabricating nonvolatile memory device 失效
    制造非易失性存储器件的方法

    公开(公告)号：US07553726B2

    公开(公告)日：2009-06-30

    申请号：US11505355

    申请日：2006-08-17

    Applicant: In-gu Yoon ,  Chul-soon Kwon ,  Jae-won Um ,  Jung-ho Moon

    Inventor： In-gu Yoon ,  Chul-soon Kwon ,  Jae-won Um ,  Jung-ho Moon

    IPC: H01L21/336 ,  H01L21/8238

    CPC classification number: H01L27/115 ,  H01L27/11521

    Abstract: A method of fabricating nonvolatile memory devices may involve forming separate floating gates on a semiconductor substrate, forming control gates on the semiconductor substrate, conformally forming a buffer film on a surface of the semiconductor substrate, injecting ions into the semiconductor substrate between the pairs of the floating gates to form a common source region partially overlapping each floating gate of the respective pair of the floating gates, depositing an insulating film on the buffer film, etching the buffer film and the insulating film at side walls of the floating gates and the control gates to form spacers at the side walls of the floating gates and the control gates, and forming a drain region in the semiconductor substrate at a side of the control gate other than a side of the control gate where the common source region is formed.

    Abstract translation: 制造非易失性存储器件的方法可以包括在半导体衬底上形成分离的浮置栅极，在半导体衬底上形成控制栅极，在半导体衬底的表面上保形地形成缓冲膜，将离子注入半导体衬底 浮置栅极，形成与各对浮置栅极的每个浮置栅极部分重叠的共同源极区域，在缓冲膜上沉积绝缘膜，在浮置栅极和控制栅极的侧壁处蚀刻缓冲膜和绝缘膜 在浮置栅极和控制栅极的侧壁处形成间隔物，并且在除了形成公共源极区域的控制栅极的一侧之外的控制栅极的一侧的半导体衬底中形成漏极区域。

    Floating gate, a nonvolatile memory device including the floating gate and method of fabricating the same
    5.
    发明申请
    Floating gate, a nonvolatile memory device including the floating gate and method of fabricating the same 审中-公开
    浮动栅极，包括浮动栅极的非易失性存储器件及其制造方法

    公开(公告)号：US20070200165A1

    公开(公告)日：2007-08-30

    申请号：US11656454

    申请日：2007-01-23

    Applicant: Young-Cheon Jeong ,  Chul-Soon Kwon ,  Jae-Min Yu ,  Jae-Hyun Park ,  Jung-Ho Moon ,  Soung-Youb Ha ,  Byeong-Cheol Lim

    Inventor： Young-Cheon Jeong ,  Chul-Soon Kwon ,  Jae-Min Yu ,  Jae-Hyun Park ,  Jung-Ho Moon ,  Soung-Youb Ha ,  Byeong-Cheol Lim

    IPC: H01L29/788

    CPC classification number: H01L29/42324 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/7885

    Abstract: Example embodiments may provide a nonvolatile memory device. The example embodiment nonvolatile memory device may include a floating gate structure formed on a semiconductor substrate with a gate insulating layer between them and/or a control gate formed adjacent to the floating gate with a tunneling insulation layer between them. The floating gate may include a first floating gate formed on the gate insulating layer, a second floating gate formed on the first floating gate with a first insulating pattern between them, and/or a gate connecting layer formed on at least one sidewall of the first insulating pattern so that the gate conducting layer may electrically connect the first floating gate and the second floating gate. The second floating gate may have a tip formed at its longitudinal end that may not contact the gate connecting layer.

    Abstract translation: 示例性实施例可以提供非易失性存储器件。 示例性实施例非易失性存储器件可以包括形成在半导体衬底上的浮置栅极结构，其间具有栅极绝缘层和/或与浮置栅极相邻形成的控制栅极，在它们之间具有隧道绝缘层。 浮置栅极可以包括形成在栅极绝缘层上的第一浮动栅极，形成在第一浮动栅极上的第二浮置栅极，其间具有第一绝缘图案，和/或形成在第一浮动栅极的至少一个侧壁上的栅极连接层 绝缘图案，使得栅极导电层可以电连接第一浮动栅极和第二浮动栅极。 第二浮栅可以在其纵向端形成有可能不接触栅极连接层的尖端。

    Method of fabricating a flash memory cell
    6.
    发明授权
    Method of fabricating a flash memory cell 有权
    制造闪存单元的方法

    公开(公告)号：US07205194B2

    公开(公告)日：2007-04-17

    申请号：US10874579

    申请日：2004-06-24

    Applicant: Yong-Sun Lee ,  Jae-Min Yu ,  Don-Woo Lee ,  Jung-Hun Cho ,  Chul-Soon Kwon ,  Jung-Ho Moon ,  In-Gu Yoon ,  Jae-Hyun Park

    Inventor： Yong-Sun Lee ,  Jae-Min Yu ,  Don-Woo Lee ,  Jung-Hun Cho ,  Chul-Soon Kwon ,  Jung-Ho Moon ,  In-Gu Yoon ,  Jae-Hyun Park

    IPC: H01L21/336

    CPC classification number: H01L29/66825 ,  H01L21/28273 ,  H01L29/42324

    Abstract: A method of fabricating a flash memory cell having a split gate structure. A sacrificial layer is formed on a floating gate layer formed on a semiconductor substrate. The sacrificial layer is etched to form an opening exposing a portion of the floating gate layer. A gate interlayer insulating layer pattern is formed inside the opening. After removing the sacrificial layer pattern and etching the floating gate layer (using the gate interlayer insulating layer pattern as an etch mask), a floating gate is formed under the gate interlayer insulating layer pattern. A control gate is formed overlapping a portion of the floating gate.

    Abstract translation: 一种制造具有分裂栅极结构的闪存单元的方法。 牺牲层形成在形成在半导体衬底上的浮栅上。 牺牲层被蚀刻以形成暴露浮动栅极层的一部分的开口。 在开口内部形成栅极层间绝缘层图案。 在去除牺牲层图案并蚀刻浮栅（使用栅极层间绝缘层图案作为蚀刻掩模）之后，在栅极层间绝缘层图案下方形成浮栅。 控制栅极形成为与浮置栅极的一部分重叠。

    Semiconductor device with split gate electrode structure and method for manufacturing the semiconductor device
    7.
    发明申请
    Semiconductor device with split gate electrode structure and method for manufacturing the semiconductor device 失效
    具有分裂栅电极结构的半导体器件和用于制造半导体器件的方法

    公开(公告)号：US20060027858A1

    公开(公告)日：2006-02-09

    申请号：US11246590

    申请日：2005-10-11

    Applicant: Jung-Ho Moon ,  Jae-Min Yu ,  Don-Woo Lee ,  Chul-Soon Kwon ,  In-Gu Yoon ,  Yong-Sun Lee ,  Jae-Hyun Park

    Inventor： Jung-Ho Moon ,  Jae-Min Yu ,  Don-Woo Lee ,  Chul-Soon Kwon ,  In-Gu Yoon ,  Yong-Sun Lee ,  Jae-Hyun Park

    IPC: H01L29/788

    CPC classification number: H01L27/11526 ,  H01L27/105 ,  H01L27/11539

    Abstract: A semiconductor device includes a substrate divided into a memory cell region and a logic region. A split gate electrode structure is formed in a memory cell region of a substrate. A silicon oxide layer is formed on a sidewall of the split gate electrode structure and a surface of the substrate. A word line is formed on the silicon oxide layer that is positioned on the sidewall of the split gate electrode structure. The word line has an upper width and a lower width. The lower width is greater than the upper width. A logic gate pattern is formed on a logic region of the substrate. The logic gate pattern has a thickness thinner than the lower width of the word line.

    Abstract translation: 半导体器件包括分为存储单元区域和逻辑区域的衬底。 在基板的存储单元区域中形成分割栅电极结构。 在分离栅电极结构的侧壁和基板的表面上形成氧化硅层。 在位于分离栅电极结构的侧壁上的氧化硅层上形成字线。 字线具有上宽度和下宽度。 较低的宽度大于上部宽度。 在基板的逻辑区域上形成逻辑门图案。 逻辑门图案具有比字线的较低宽度更薄的厚度。

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