公开(公告)号：US09312260B2

公开(公告)日：2016-04-12

申请号：US13086186

申请日：2011-04-13

Applicant: Ali Keshavarzi ,  Ta-Pen Guo ,  Helen Shu-Hui Chang ,  Hsiang-Jen Tseng ,  Shyue-Shyh Lin ,  Lee-Chung Lu ,  Chung-Cheng Wu ,  Li-Chun Tien ,  Jung-Chan Yang ,  Shu-Min Chen ,  Min Cao ,  Yung-Chin Hou

Inventor： Ali Keshavarzi ,  Ta-Pen Guo ,  Helen Shu-Hui Chang ,  Hsiang-Jen Tseng ,  Shyue-Shyh Lin ,  Lee-Chung Lu ,  Chung-Cheng Wu ,  Li-Chun Tien ,  Jung-Chan Yang ,  Shu-Min Chen ,  Min Cao ,  Yung-Chin Hou

IPC: H01L29/76 ,  H01L27/092 ,  H01L21/8238 ,  H01L23/485 ,  H01L27/02 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/092 ,  H01L21/823871 ,  H01L23/485 ,  H01L27/0207 ,  H01L29/0649 ,  H01L29/4238 ,  H01L29/495 ,  H01L29/66545 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit includes a first diffusion area for a first type transistor. The first type transistor includes a first drain region and a first source region. A second diffusion area for a second type transistor is separated from the first diffusion area. The second type transistor includes a second drain region and a second source region. A gate electrode continuously extends across the first diffusion area and the second diffusion area in a routing direction. A first metallic structure is electrically coupled with the first source region. A second metallic structure is electrically coupled with the second drain region. A third metallic structure is disposed over and electrically coupled with the first and second metallic structures. A width of the first metallic structure is substantially equal to or larger than a width of the third metallic structure.

Abstract translation: 集成电路包括用于第一类型晶体管的第一扩散区域。 第一类型晶体管包括第一漏极区域和第一源极区域。 用于第二类型晶体管的第二扩散区域与第一扩散区域分离。 第二类型晶体管包括第二漏极区域和第二源极区域。 栅电极在布线方向上连续延伸穿过第一扩散区域和第二扩散区域。 第一金属结构与第一源区电耦合。 第二金属结构与第二漏区电耦合。 第三金属结构设置在第一和第二金属结构之上并与第一和第二金属结构电耦合。 第一金属结构体的宽度基本上等于或大于第三金属结构体的宽度。

公开(公告)号：US07749911B2

公开(公告)日：2010-07-06

申请号：US11001514

申请日：2004-11-30

Applicant: Chung-Cheng Wu ,  Wen-Ting Chu

Inventor： Chung-Cheng Wu ,  Wen-Ting Chu

IPC: H01L21/311

CPC classification number: H01L21/28114 ,  H01L21/31116 ,  H01L29/42376 ,  H01L29/66575

Abstract: A T-shaped gate structure and method for forming the same the method including providing a semiconductor substrate comprising at least one overlying sacrificial layer; lithographically patterning a resist layer overlying the at least one sacrificial layer for etching an opening; forming the etched opening through a thickness of the at least one sacrificial layer to expose the semiconductor substrate, said etched opening comprising a tapered cross section having a wider upper portion compared to a bottom portion; and, backfilling the etched opening with a gate electrode material to form a gate structure.

Abstract translation: 一种T形栅极结构及其形成方法，包括提供包括至少一个上覆牺牲层的半导体衬底; 光刻地图案化覆盖至少一个牺牲层的抗蚀剂层，以蚀刻开口; 通过所述至少一个牺牲层的厚度形成所述蚀刻开口以暴露所述半导体衬底，所述蚀刻开口包括与底部相比具有较宽上部的锥形横截面; 并且用栅电极材料回填蚀刻的开口以形成栅极结构。

公开(公告)号：US20090302911A1

公开(公告)日：2009-12-10

申请号：US12347074

申请日：2008-12-31

Applicant: Chen-Hsung Wang ,  Wei-Liang Kung ,  Chung-Cheng Wu

Inventor： Chen-Hsung Wang ,  Wei-Liang Kung ,  Chung-Cheng Wu

IPC: H03K3/017

CPC classification number: H03K3/017 ,  H03K3/84 ,  H03K4/502

Abstract: A frequency jitter generator and a frequency jitter PWM controller are provided for overcoming the shortcoming that a conventional PWM controller reduces the electromagnetic interference issue by means of varying the operating frequency of the PWM controller based on an input voltage, while resulting in the uncertainty of the range of frequency jitter and the difficulty circuit design due to the effect of the input voltage and the load. The frequency jitter generator and PWM controller adjust the range of frequency jitter by using a signal within a fixed voltage range. The invention not only gets rid of the effect of the input voltage and the loading, but also simplifies the circuit design by fixing the range of frequency jitter no greater than a predetermined percentage regardless of the operating frequency of the PWM controller.

Abstract translation: 提供了一种频率抖动发生器和频率抖动PWM控制器来克服传统PWM控制器通过基于输入电压改变PWM控制器的工作频率来减少电磁干扰问题的缺点，同时导致不确定性 由于输入电压和负载的影响，频率抖动范围和电路设计难度大。 频率抖动发生器和PWM控制器通过使用固定电压范围内的信号来调整频率抖动的范围。 本发明不仅消除了输入电压和负载的影响，而且通过将频率抖动的范围固定为不大于预定百分比来简化电路设计，而不管PWM控制器的工作频率如何。

公开(公告)号：US20080074914A1

公开(公告)日：2008-03-27

申请号：US11859721

申请日：2007-09-21

Applicant: Hong-Gee FANG ,  Wen-Chieh LEE ,  Ching-Wen CHEN ,  Chih-Yuan CHENG ,  Chung-Cheng WU

Inventor： Hong-Gee FANG ,  Wen-Chieh LEE ,  Ching-Wen CHEN ,  Chih-Yuan CHENG ,  Chung-Cheng WU

IPC: G11C5/02 ,  G11C7/02

CPC classification number: G11C11/4091 ,  G11C5/025 ,  G11C7/065 ,  G11C7/12 ,  G11C11/4094

Abstract: A memory device comprises a first memory cell and a second memory cell. The first memory cell includes a first transistor coupled to a bit line and the second memory cell includes a second transistor coupled to a bit line bar. The first transistor includes a first gate terminal coupled to a first word line. The second transistor includes a second gate terminal coupled to a second word line. The first transistor and the second transistor are controlled by the first word line and the second word line respectively. A first sense amplifier having an asymmetric configuration is coupled to the bit line and the bit line bar and is capable to sense a status of at least one of the bit line and the bit line bar.

Abstract translation: 存储器件包括第一存储单元和第二存储单元。 第一存储单元包括耦合到位线的第一晶体管，并且第二存储单元包括耦合到位线条的第二晶体管。 第一晶体管包括耦合到第一字线的第一栅极端子。 第二晶体管包括耦合到第二字线的第二栅极端子。 第一晶体管和第二晶体管分别由第一字线和第二字线控制。 具有不对称配置的第一读出放大器耦合到位线和位线条，并且能够感测位线和位线条中的至少一个的状态。

公开(公告)号：US07071515B2

公开(公告)日：2006-07-04

申请号：US10619114

申请日：2003-07-14

Applicant: Yi-Ming Sheu ,  Da-Wen Lin ,  Cheng-Ku Chen ,  Po-Ying Yeh ,  Shi-Shung Peng ,  Chung-Cheng Wu

Inventor： Yi-Ming Sheu ,  Da-Wen Lin ,  Cheng-Ku Chen ,  Po-Ying Yeh ,  Shi-Shung Peng ,  Chung-Cheng Wu

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC classification number: H01L21/823481 ,  H01L21/26586 ,  H01L21/76237

Abstract: A method to reduce the inverse narrow width effect in NMOS transistors is described. An oxide liner is deposited in a shallow trench that is formed to isolate active areas in a substrate. A photoresist plug is formed in the shallow trench and is recessed below the top of the substrate to expose the top portion of the oxide liner. An angled indium implant through the oxide liner into the substrate is then performed. The plug is removed and an insulator is deposited to fill the trenches. After planarization and wet etch steps, formation of a gate dielectric layer and a patterned gate layer, the NMOS transistor exhibits an improved Vt roll-off of 40 to 45 mVolts for both long and short channels. The improvement is achieved with no degradation in junction or isolation performance. The indium implant dose and angle may be varied to provide flexibility to the process.

Abstract translation: 描述了一种在NMOS晶体管中减小反向窄宽度效应的方法。 氧化物衬垫沉积在形成为隔离衬底中的有源区域的浅沟槽中。 在浅沟槽中形成光致抗蚀剂插塞，并且在衬底的顶部下方凹入以暴露氧化物衬垫的顶部部分。 然后进行通过氧化物衬垫到衬底中的成角度的铟植入物。 去除插头并沉积绝缘体以填充沟槽。 在平坦化和湿蚀刻步骤之后，形成栅极介电层和图案化栅极层，NMOS晶体管对于长沟道和短沟道都表现出改善的Vt滚降为40至45毫伏。 在不会降低结或隔离性能的情况下实现改进。 可以改变铟注入剂量和角度以提供该过程的灵活性。

公开(公告)号：US07047348B2

公开(公告)日：2006-05-16

申请号：US10128471

申请日：2002-04-22

Applicant: Chung-Cheng Wu

Inventor： Chung-Cheng Wu

IPC: G06F13/36 ,  G06F13/00 ,  G06F13/14 ,  G06F13/20

CPC classification number: G06F13/4027

Abstract: A method and an architecture for accessing hardware devices in a computer system and the chipset thereof are provided. A bi-directional two-wired serial interface, for instance, a system management bus (SMB), is configured to connect an I/O device, such as a local area network adapter, to a system controller such as a southbridge or a northbridge chipset. The I/O device which includes a SMB master controller serves as a SMB master device for generating a clock signal and transmitting a data signal defined by the SMB protocol to the system controller according to the clock signal. The system controller which includes a PCI master and a SMB slave controller serves as a SMB slave device for receiving commands and data bytes in the data signal from the SMB master device to drive the PCI master to access the register block of peripherals and system memory of the computer system.

Abstract translation: 提供了一种用于访问计算机系统中的硬件设备及其芯片组的方法和架构。 双向双向串行接口，例如系统管理总线（SMB）被配置为将诸如局域网适配器的I / O设备连接到诸如南桥或北桥的系统控制器 芯片组。 包括SMB主控制器的I / O设备用作用于产生时钟信号并根据时钟信号将由SMB协议定义的数据信号发送到系统控制器的SMB主设备。 包括PCI主机和SMB从控制器的系统控制器用作SMB从设备，用于从SMB主设备接收数据信号中的命令和数据字节，以驱动PCI主机访问外设寄存器块和系统存储器 计算机系统。

公开(公告)号：US06777280B2

公开(公告)日：2004-08-17

申请号：US10136498

申请日：2002-04-30

Applicant: Li-Chun Li ,  Huoy-Jong Wu ,  Chung-Cheng Wu ,  Saysamone Pittikoun ,  Wen-Wei Lo

Inventor： Li-Chun Li ,  Huoy-Jong Wu ,  Chung-Cheng Wu ,  Saysamone Pittikoun ,  Wen-Wei Lo

IPC: H01L218238

CPC classification number: H01L27/10894 ,  H01L21/761 ,  H01L21/76202 ,  H01L27/10897

Abstract: Dynamic Random Access Memory (DRAM) cells are formed in a P well formed in a biased deep N well (DNW). PMOS transistors are formed in N wells. The NMOS channels stop implant mask is modified not to be a reverse of the N well mask in order to block the channels stop implant from an N+ contact region used for DNW biasing. In DRAMs and other integrated circuits, a minimal spacing requirement between a well of an integrated circuit on the one hand and adjacent circuitry on the other hand is eliminated by laying out the adjacent circuitry so that the well is located adjacent to a transistor having an electrode connected to the same voltage as the voltage that biases the well. For example, in DRAMs, the minimal spacing requirement between the DNW and the read/write circuitry is eliminated by locating the DNW next to a transistor precharging the bit lines before memory accesses. One electrode of the transistor is connected to a precharge voltage. This electrode overlaps the DNW which is biased to the same precharge voltage. This electrode provides the DNW N+ contact region.

公开(公告)号：US5633520A

公开(公告)日：1997-05-27

申请号：US667609

申请日：1996-06-21

Applicant: Chung-Cheng Wu ,  Ming-Tzong Yang

Inventor： Chung-Cheng Wu ,  Ming-Tzong Yang

IPC: H01L21/822 ,  H01L27/115 ,  H01L27/108 ,  H01L29/76 ,  H01L29/788

CPC classification number: H01L27/115 ,  H01L21/8221 ,  H01L29/788 ,  Y10S148/116 ,  Y10S148/117 ,  Y10S148/163 ,  Y10S438/981

Abstract: An MOSFET device is fabricated with a plurality of conductors capacitively coupled to a first electrode, forming a mask on the surface of the first electrode exposing a predetermined zone of the first electrode, doping the first electrode through the mask, removing the mask from the surface of the first electrode, oxidizing the first electrode to form a layer of oxide over the first electrode with a thicker layer of oxide over the predetermined zone and a thinner layer of oxide elsewhere, forming at least one electrode over the first electrode on the thinner layer of oxide outside of the zone and forming at least one other electrode over the first electrode on the thicker layer of oxide inside the zone, whereby the one electrode and the other electrode have substantially different capacitive coupling to the electrode.

Abstract translation: 制造具有电容耦合到第一电极的多个导体的MOSFET器件，在第一电极的表面上形成掩模，暴露第一电极的预定区域，通过掩模掺杂第一电极，从表面去除掩模 在所述第一电极上氧化所述第一电极以在所述第一电极上形成氧化层以在所述预定区域上具有较厚的氧化物层，并且在其它地方形成更薄的氧化物层，在所述较薄层上的所述第一电极上形成至少一个电极 的氧化物，并且在所述区域内的更厚的氧化物层上在所述第一电极上方形成至少一个其它电极，由此所述一个电极和所述另一个电极具有与所述电极基本上不同的电容耦合。

公开(公告)号：US08278179B2

公开(公告)日：2012-10-02

申请号：US12720476

申请日：2010-03-09

Applicant: Da-Wen Lin ,  Che-Min Chu ,  Tsung-Hung Li ,  Chih-Hung Tseng ,  Yen-Chun Lin ,  Chung-Cheng Wu

Inventor： Da-Wen Lin ,  Che-Min Chu ,  Tsung-Hung Li ,  Chih-Hung Tseng ,  Yen-Chun Lin ,  Chung-Cheng Wu

IPC: H01L21/336

CPC classification number: H01L29/66795 ,  H01L21/823821

Abstract: A method of forming a semiconductor structure includes providing a substrate including a fin at a surface of the substrate, and forming a fin field-effect transistor (FinFET), which further includes forming a gate stack on the fin; forming a thin spacer on a sidewall of the gate stack; and epitaxially growing a epitaxy region starting from the fin. After the step of epitaxially growing the epitaxy region, a main spacer is formed on an outer edge of the thin spacer. After the step of forming the main spacer, a deep source/drain implantation is performed to form a deep source/drain region for the FinFET.

Abstract translation: 一种形成半导体结构的方法包括在衬底的表面提供包括鳍的衬底，以及形成鳍状场效应晶体管（FinFET），其还包括在鳍上形成栅叠层; 在所述栅极堆叠的侧壁上形成薄的间隔物; 并从翅片开始外延生长外延区域。 在外延生长外延区域的步骤之后，在间隔物的外边缘上形成主间隔物。 在形成主间隔物的步骤之后，进行深源极/漏极注入以形成用于FinFET的深源极/漏极区域。

公开(公告)号：US20120135575A1

公开(公告)日：2012-05-31

申请号：US13042539

申请日：2011-03-08

Applicant: King-Yuen WONG ,  Ming-Lung CHENG ,  Chien-Tai CHAN ,  Da-Wen LIN ,  Chung-Cheng WU

Inventor： King-Yuen WONG ,  Ming-Lung CHENG ,  Chien-Tai CHAN ,  Da-Wen LIN ,  Chung-Cheng WU

IPC: H01L21/336

CPC classification number: H01L29/7833 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7834

Abstract: A method of forming an integrated circuit includes forming a gate structure over a substrate. Portions of the substrate are removed to form recesses adjacent to the gate structure. A dopant-rich layer having first type dopants is formed on a sidewall and a bottom of each of the recesses. A silicon-containing material structure is formed in each of the recesses. The silicon-containing material structure has second type dopants. The second type dopants are opposite to the first type dopants.

Abstract translation: 形成集成电路的方法包括在衬底上形成栅极结构。 去除基板的一部分以形成与栅极结构相邻的凹部。 在每个凹部的侧壁和底部形成有具有第一类型掺杂剂的富掺杂层。 在每个凹部中形成含硅材料结构。 含硅材料结构具有第二种掺杂剂。 第二种掺杂剂与第一种掺杂剂相反。